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參數(shù)資料
| 型號： | 82C205 |
| 英文描述： | Consumer IC |
| 中文描述： | 消費性IC |
| 文件頁數(shù)： | 27/47頁 |
| 文件大?。?/td> | 460K |
| 代理商： | 82C205 |
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Advance Information
82C205
912-1000-024
Revision 1.0
Page 23
7
6
5
4
3
2
1
0
Index 32h
Blink Rate for OSD (R/W)
Default = 00h
Blink Rate for On Screen Display.
Blink Rate is in units of frames. Setting the blink rate to 30 means
that the OSD will appear for 30 frames, then disappear for 30 frames.
The OSD will blink only if the blink attribute is selected
Index 33h - 37h
Reserved
Default = 00h
5.5. Dither Register Settings
7
6
5
4
3
2
1
0
Index 38h
Primary Bits (R/W)
Default = 00h
Capture Data Bits:
Bits per pixel color component for dither capture data.
Reserved
(set to 0)
Dither Line Depth Select:
For TFT:
Dither Line Depth =
(8 - Primary Bits) / 2
Index 39h
Dither Control (R/W)
Default = FAh
Reserved
(set to 1)
Reserved
(set to 1)
Reserved
(set to 1)
Reserved
(set to 1)
Reserved
(set to 2)
Reserved
(set to 2)
Index 3Ah
Dither Threshold (R/W)
Default = 00h
Adjustment of this value can reduce Moire pattern effects.
Index 3Bh
Dither Algorithm Initializations (R/W)
Default = 03h
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
(set to 1)
Reserved
(set to 1)
Index 3Ch
Dither Frame and Line Offset (R/W)
Default = 00h
Reserved
Dither Line Offset Function Control:
This register setting depends on the values in Register
38h, the Primary Bits, and the Dither Line Depth.
8 - Primary Bits - Dither Line Depth
Index 3Dh
Dither Mode (R/W)
Default = 00h
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Index 3Eh - 3Fh
Reserved
Default = 00h
5.6. Capture CRTC Registers
7
6
5
4
3
2
1
0
Index 40h
Capture Horizontal Sync Width (R/W)
Default = 00h
Capture Horizontal Sync Width (in units of VCLK1 cycles).
Low Byte
Index 41h
Capture Horizontal Sync Width (R/W)
Default = 00h
Reserved
Reserved
Reserved
Reserved
High Byte
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