參數(shù)資料
型號： 82845GE
廠商： Intel Corp.
英文描述： 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)
中文描述： 82845GE圖形和內存控制器中樞（GMCH）和82845PE內存控制器中樞（MCH）
文件頁數(shù)： 22/157頁
文件大小： 1407K
代理商： 82845GE
Intel
82845MP/82845MZ Chipset-Mobile (MCH-M)
22
Datasheet
250687-002
R
Signal Name
Type
Description
HD[63:0]#
I/O
AGTL+ 4x
Host Data:
These signals are connected to the system data bus.
HD[63:0]#
are
transferred at 4x rate. Note that the data signals are inverted on the system bus.
HDSTBP[3:0]#
HDSTBN[3:0]#
I/O
AGTL+ 4x
Differential Host Data Strobes:
The differential source synchronous strobes used
to transfer
HD[63:0]#
and
DBI[3:0]#
at the 4x transfer rate.
HDSTBP3#, HDSTBN3#
HDSTBP2#, HDSTBN2#
HDSTBP1#, HDSTBN1#
HDSTBP0#, HDSTBN0#
Strobe
Data Bits
HD[63:48]#, DBI3#
HD[47:32]#, DBI2#
HD[31:16]#, DBI1#
HD[15:0]#, DBI0#
HIT#
I/O
AGTL+
Hit:
Indicates that a caching agent holds an unmodified version of the requested
line. Also, driven in conjunction with
HITM#
by the target to extend the snoop
window.
HITM#
I/O
AGTL+
Hit Modified:
Indicates that a caching agent holds a modified version of the
requested line and that this agent assumes responsibility for providing the line.
Also, driven in conjunction with
HIT#
to extend the snoop window.
HLOCK#
I
AGTL+
Host Lock:
All system bus cycles sampled with the assertion of
HLOCK#
and
ADS#
, until the negation of
HLOCK#
must be atomic, i.e.
no hub interface or
AGP snoopable access
to DRAM are allowed when
HLOCK#
is asserted by the
processor.
HREQ[4:0]#
I/O
AGTL+ 2x
Host Request Command:
Defines the attributes of the request. In Enhanced
Mode
HREQ[4:0]#
are transferred at 2x rate. Asserted by the requesting agent
during both halves of Request Phase. In the first half the signals define the
transaction type to a level of detail that is sufficient to begin a snoop request. In the
second half the signals carry additional information to define the complete
transaction type.
The transactions supported by the MCH-M Host Bridge are defined in the Host
Interface section of this document.
HTRDY#
O
AGTL+
Host Target Ready:
Indicates that the target of the processor transaction is able
to enter the data transfer phase.
RS[2:0]#
O
AGTL+
Response Status:
Indicates type of response according to the following the table:
RS[2:0]
000
001
010
011
100
101
110
111
Response type
Idle state
Retry response
Deferred response
Reserved (not driven by MCH-M)
Hard Failure (not driven by MCH-M)
No data response
Implicit Write back
Normal data response
相關PDF資料
PDF描述
8284A Clock Generator and Driver for 8066, 8088 Processors
8284A-1 Clock Generator and Driver for 8066, 8088 Processors
8284 TWO-OUTPUT LNB SUPPLY AND CONTROL-VOLTAGE REGULATOR
82865G Intel 865G/865GV Graphics and Memory Controller Hub
82865GV Intel 865G/865GV Graphics and Memory Controller Hub
相關代理商/技術參數(shù)
參數(shù)描述
82845GL 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH)
82845GV 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH)
82845GX 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH)
82845MP 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)
82845MX 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)
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