- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378217 > 82845GE (Intel Corp.) 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH) PDF資料下載
參數(shù)資料
| 型號： | 82845GE |
| 廠商： | Intel Corp. |
| 英文描述： | 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH) |
| 中文描述： | 82845GE圖形和內(nèi)存控制器中樞（GMCH）和82845PE內(nèi)存控制器中樞（MCH） |
| 文件頁數(shù)： | 113/157頁 |
| 文件大?。?/td> | 1407K |
| 代理商： | 82845GE |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁當(dāng)前第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁
Intel
82845MP/82845MZ Chipset-Mobile (MCH-M)
250687-002
Datasheet
113
R
All memory read and write accesses to Main DRAM (except SMM space).
All memory write accesses from the hub interface A to AGP memory range defined by MBASE1,
MLIMIT1, PMBASE1, and PMLIMIT1.
All memory read/write accesses to the Graphics Aperture defined by APBASE and APSIZE.
Memory writes to VGA range on AGP if enabled.
All memory reads from the hub interface A that are targeted > 4 GB memory range will be terminated
with Master Abort completion, and all memory writes (>4 GB) from the hub interface A will be ignored.
4.5.2.
AGP Interface Decode Rules
Cycles Initiated Using AGP FRAME# Protocol
The MCH-M does not support any AGP FRAME# access targeting the hub interface A. The MCH-M
will claim AGP initiated memory read and write transactions decoded to the main DRAM range or the
Graphics Aperture range. All other memory read and write requests will be master-aborted by the AGP
initiator as a consequence of MCH-M not responding to a transaction.
The MCH-M forwards AGP/PCI accesses addressed to the DOS Compatibility ranges between
0C0000h-0FFFFFh to main memory, regardless of the configuration of the Programmable Attributes
Map registers (PAM registers). The PAM registers govern the destination of host CPU accesses to the
DOS Compatibility ranges but do not similarly affect the destination of AGP/PCI accesses to this range.
MCH-M will forward to main memory any AGP/PCI initiated access to the PAM areas. Note that the
MCH-M may hang if an AGP originated access occurs to a Read Disabled or Write Disabled PAM
segment. Therefore, the following critical restriction is placed on the programming of the PAM regions:
at the time that an AGP accesses to a PAM region occurs, the targeted PAM segment must be
programmed to be both readable and writable. If an AGP master issues an I/O, PCI Configuration or PCI
Special Cycle transaction, the MCH-M will not respond and cycle will result in a master-abort.
Cycles Initiated Using AGP PIPE# or SBA Protocol
All cycles must reference main memory i.e. main DRAM address range (including PAM) or Graphics
Aperture range (also physically mapped within DRAM but using different address range). AGP accesses
to SMM space are not allowed. AGP protocol cycles that target DRAM are not snooped on the host bus,
even if they fall outside of the AGP aperture range.
If a cycle is outside of main memory range then it will terminate as follows:
Reads: remapped to memory address 0h, data returned from address 0h, and IAAF error bit set in
ERRSTS register in device #0
Writes: dropped “on the floor” i.e. terminated internally without affecting any buffers or main
memory
AGP Accesses to MCH-M that Cross Device Boundaries
The MCH-M will disconnect AGP FRAME# transactions on 4KB boundaries.
AGP PIPE# and SBA accesses are limited to 256 bytes and must hit DRAM. Read accesses crossing out
of DRAM will return invalid data, and the IAAF Error bit will be set. Write accesses crossing out of
DRAM will be discarded, and the IAAF Error bit will be set.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 8284A | Clock Generator and Driver for 8066, 8088 Processors |
| 8284A-1 | Clock Generator and Driver for 8066, 8088 Processors |
| 8284 | TWO-OUTPUT LNB SUPPLY AND CONTROL-VOLTAGE REGULATOR |
| 82865G | Intel 865G/865GV Graphics and Memory Controller Hub |
| 82865GV | Intel 865G/865GV Graphics and Memory Controller Hub |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 82845GL | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH) |
| 82845GV | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH) |
| 82845GX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel 82845G/82845GL/82845GV Graphics and Memory Controller Hub (GMCH) |
| 82845MP | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M) |
| 82845MX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。