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參數(shù)資料
| 型號(hào)： | 82595FX |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | ISA BUS HIGH INTEGRATION ETHERNET CONTROLLER |
| 中文描述： | 1 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP16 |
| 封裝： | QFP-160 |
| 文件頁數(shù)： | 14/54頁 |
| 文件大小： | 643K |
| 代理商： | 82595FX |
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82595FX
prefetch mechanism to the local SRAM so that the
data is always available to the CPU as either an 8- or
16-bit word. In the case of the CPU reading from the
SRAM, the 82595FX reads the next two bytes from
the SRAM, the 82595FX between CPU cycles so
that the data is always available as a word in the
82595FX’s Local Memory IO Port register. In the
case of the CPU writing to the SRAM, the data is
written into the 82595FX’s Local Memory IO Port
then transferred to the SRAM by the 82595FX be-
tween CPU cycles. This prefetch mechanism of the
82595FX allows for IO read and writes to the local
memory to be performed with no additional wait-
states (3 clocks per data transfer cycle).
The DMA unit provides addressing and control to
move RCV or XMT data between the 82595FX and
the local SRAM. For transmission, the CPU is re-
quired only to copy the data to the local memory,
initialize the 82595FX’s DMA Current Address Reg-
ister (CAR) to point to the beginning of the frame,
and issue a Transmit Command to the 82595FX.
The DMA unit facilitates the transfers from the local
memory to the 82595FX as transmission takes
place. The DMA unit will reset upon collision during
a transmission, enabling automatic re-transmission
of the transmit frame. During reception, the DMA
unit implements a recyclable ring buffer structure
which can receive continuous back to back frames
without CPU intervention on a per frame basis (see
Section 8.2 for details).
The 82595FX provides address decoding and con-
trol to allow access to an external Boot EPROM/
FLASH if these components are utilized in an
82595FX design. The 82595FX also provides an in-
terface to a serial EEPROM to replace jumper
blocks used to contain configuration information.
This port is used to store configuration information
and in addition, it is used to store Plug N’ Play infor-
mation as defined in the Plug N’ Play Specification.
The 82595FX arbitrates accesses to the local mem-
ory sub-system by the CPU and the 82595FX. The
arbitration unit will hold off an 82595FX DMA cycle
to the local memory if a CPU cycle is already in prog-
ress. Likewise, it will hold off the CPU if an 82595FX
cycle is already in progress. The cycle which is held
off will be completed on termination of the preceding
cycle.
3.3 CSMA/CD Unit
The CSMA/CD unit implements the IEEE 802.3
CSMA/CD protocol. It performs such functions as
transmission deferral to link traffic, interframe spac-
ing, exponential backoff for collision handling, ad-
dress recognition, etc. The CSMA/CD unit serves as
the interface between the local memory and the se-
rial interface. It serializes data transferred from the
local memory before it is passed to the serial inter-
face unit for transmission. During frame reception, it
converts the serial data received from the serial in-
terface to a byte format before it is transferred to
local memory. The CSMA/CD unit strips framing pa-
rameters such as the Preamble and SFD fields be-
fore the frame is passes to memory for reception.
For transmission, the CSMA/CD unit builds the
frame format before the frame is passed to the serial
interface for transmission.
3.4 Serial Interface
The 82595FX’s serial interface provides either an
AUI port interface or a Twisted Pair Ethernet (TPE)
interface. The AUI port can be connected to an
Ethernet Transceiver cable drop to provide a fully
compliant IEEE 802.3 AUI interface. The AUI port
can also interface to a transceiver device to
provide a fully compliant IEEE 802.3 10BASE2
(Cheapernet) interface. The TPE port provides a ful-
ly compliant 10BASE-T interface. The 82595FX au-
tomatically enables either to the AUI or TPE inter-
face depending on which medium is connected to
the chip. Software configuration can override this
automatic selection.
4.0
ACCESSING THE 82595FX
All access to the 82595FX is made through one of
three banks of IO registers. Each bank contains 16
registers. Each register in a bank is directly accessi-
ble via addressing. Through the use of bank switch-
ing, the 82595FX utilizes only 16 IO locations in the
host system’s IO map to access each of its regis-
ters. The different banks are accessed by setting the
POINTER field in the 82595FX Command Register
to select each bank. The Command Register is Reg-
ister for each bank.
4.1 82595FX Register Map
The 82595FX registers are contained in three banks
of 16 IO registers per bank. These three banks are
shown in the following three pages.
14
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 82595TX | ISA/PCMCIA HIGH INTEGRATION ETHERNET CONTROLLER |
| 82596DX | HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR |
| 82596SX | HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR |
| 82596CA | HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR |
| 8261SHAKE22 | Alternate Action and Momentary Pushbutton Switches |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 82595TX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:ISA/PCMCIA HIGH INTEGRATION ETHERNET CONTROLLER |
| 82596 | 制造商:TE Connectivity 功能描述:STD TERM/SPLICE WALL CHART - Bulk |
| 82596CA | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR |
| 82596DX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR |
| 82596SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR |
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