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參數(shù)資料
| 型號： | 79RC32K438300BBI |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | IDTTM InterpriseTM Integrated Communications Processor |
| 中文描述： | IDTTM InterpriseTM集成通信處理器 |
| 文件頁數(shù)： | 36/59頁 |
| 文件大?。?/td> | 644K |
| 代理商： | 79RC32K438300BBI |
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36 of 59
May 25, 2004
IDT 79RC32438
Figure 22 JTAG AC Timing Waveform
The IEEE 1149.1 specification requires that the JTAG and EJTAG TAP controllers be reset at power-up whether or not the interfaces are used for
a boundary scan or a probe. Reset can occur through a pull-down resistor on JTAG_TRST_N if the probe is not connected. However, on-chip pull-up
resistors are implemented on the RC32438 due to an IEEE 1149.1 requirement. Having on-chip pull-up and external pull-down resistors for the
JTAG_TRST_N signal requires special care in the design to ensure that a valid logical level is provided to JTAG_TRST_N, such as using a small
external pull-down resistor to ensure this level overrides the on-chip pull-up. An alternative is to use an active power-up reset circuit for
JTAG_TRST_N, which drives JTAG_TRST_N low only at power-up and then holds JTAG_TRST_N high afterwards with a pull-up resistor.
Figure 23 shows the electrical connection of the EJTAG probe target system connector.
Figure 23 Target System Electrical EJTAG Connection
Tpw_16d
Tdz_16c
Tdo_16c
Thld_16e
Tsu_16e
Thld_16b
Tsu_16b
Thld_16b
Tsu_16b
Tlow_16a
Tper_16a
Thigh_16a
JTAG_TCK
JTAG_TDI
JTAG_TMS
EJTAG_TMS
JTAG_TDO
JTAG_TRST_N
GND
GND
GND
GND
GND
1
TRST*
TDI
TDO
TMS
TCK
RST*
DINT
no connect
JTAG_TRST_N
JTAG_TDI
JTAG_TDO
EJTAG_TMS
JTAG_TCK
GND
VDD
GND
VccIO voltage
reference
P
P
Series-res.
COLDRSTN
or RSTN
Target System
Reset Circuit
P
Other reset
sources
RC32438
VSENSE
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相關代理商/技術參數(shù) |
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| 79RC32T335-133DH | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|32-BIT|QFP|208PIN|PLASTIC |
| 79RC32T335-133DHI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|32-BIT|QFP|208PIN|PLASTIC |
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| 79RC32T335-150DHI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|32-BIT|QFP|208PIN|PLASTIC |
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