參數(shù)資料
型號(hào): 79RC32K438300BBI
廠商: Integrated Device Technology, Inc.
英文描述: IDTTM InterpriseTM Integrated Communications Processor
中文描述: IDTTM InterpriseTM集成通信處理器
文件頁數(shù): 33/59頁
文件大?。?/td> 644K
代理商: 79RC32K438300BBI
33 of 59
May 25, 2004
IDT 79RC32438
Figure 18 SPI AC Timing Waveform — PCI Configurations Load
Signal
Symbol
Reference
Edge
200MHz
233MHz
266MHz
300MHz
Unit
Conditions
Timing
Diagram
Reference
Min
Max
Min
Max
Min
Max
Min
Max
SPI
1
1.
In SPI mode, the SCK period and sampling edge are programmable. In PCI mode, the SCK period is fixed and the sampling edge is rising.
2.
PCIEECS is the PCI serial EEPROM chip select. It is an alternate function of PCIGNTN[1].
3.
In Bit I/O mode, SCK, SDI, and SDO must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous.
SCK
Tper_15a
None
1920
1920
1920
1920
ns
33 MHz PCI
See Figures 18,
19, 20 and 21.
Tper_15a
960
960
960
960
ns
66 MHz PCI
Tper_15a
100
166667
100
166667
100
166667
100
166667
ns
SPI
Thigh_15a,
Tlow_15a
930
990
930
990
930
990
930
990
ns
33 MHz PCI
Thigh_15a,
Tlow_15a
465
495
465
495
465
495
465
495
ns
66 MHz PCI
Thigh_15a,
Tlow_15a
40
83353
40
83353
40
83353
40
83353
ns
SPI
SDI
Tsu_15b
SCK rising or
falling
60
60
60
60
ns
SPI or PCI
Thld_15b
60
60
60
60
ns
SDO
Tdo_15c
SCK rising or
falling
0
60
0
60
0
60
0
60
ns
SPI or PCI
PCIEECS
2
Tdo_15d
SCK rising or
falling
0
60
0
60
0
60
0
60
ns
PCI
SCK, SDI, SDO
3
Tpw_15e
None
2(ICLK)
2(ICLK)
2(ICLK)
2(ICLK)
ns
Bit I/O
Table 13 SPI AC Timing Characteristics
Tdo_15c
bit 6
Tdo_15d
Thld_15b
Tsu_15b
Tlow_15a
Thigh_15a
Tper_15a
MSB
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
LSB
Loading PCI configuration registers through SPI from an EEPROM.
MSB
bit 4
bit 2
LSB
bit 5
bit 3
bit 1
SCK
PCIEECS
SDI
SDO
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