參數(shù)資料
型號(hào): 79RC32K438300BBI
廠商: Integrated Device Technology, Inc.
英文描述: IDTTM InterpriseTM Integrated Communications Processor
中文描述: IDTTM InterpriseTM集成通信處理器
文件頁(yè)數(shù): 27/59頁(yè)
文件大?。?/td> 644K
代理商: 79RC32K438300BBI
27 of 59
May 25, 2004
IDT 79RC32438
Figure 11 DMAREQN AC Timing Waveform
Signal
Symbol
Reference
Edge
200MHz
233MHz
266MHz
300MHz
Unit
Conditions
Timing
Diagram
Reference
Min
Max
Min
Max
Min
Max
Min
Max
Ethernet
1
1.
There are two MII interfaces and the timing is the same for each. “X” represents interface 0 or 1.
2.
The values for this symbol were determined by calculation, not by testing.
MIIMDC
Tper_9a
None
40.0
33.3
30.0
30.0
ns
See Figure 12.
Thigh_9a,
Tlow_9a
16.0
13.0
12.0
12.0
ns
MIIMDIO
Tsu_9b
MIIMDC rising
10.0
10.0
10.0
10.0
ns
Thld_9b
0.0
0.0
0.0
0.0
ns
Tdo_9b
2
10
300
10
300
10
300
10
300
ns
MIIxRXCLK,
MIIxTXCLK
3
Tper_9c
None
399.96 400.4 399.96 400.4 399.96 400.4 399.96 400.4
ns
10 Mbps
Thigh_9c,
Tlow_9c
140
260
140
260
140
260
140
260
ns
Trise_9c,
Tfall_9c
3.0
3.0
3.0
3.0
ns
MIIxRXCLK,
MIIxTXCLK
3
Tper_9d
None
39.9
40.0
39.9
40.0
39.9
40.0
39.9
40.0
ns
100 Mbps
Thigh_9d,
Tlow_9d
14.0
26.0
14.0
26.0
14.0
26.0
14.0
26.0
ns
Trise_9d,
Tfall_9d
2.0
2.0
2.0
2.0
ns
MIIxRXD[3:0],
MIIxRXDV,
MIIxRXER
Tsu_9e
MIIxRXCLK
rising
10.0
10.0
10.0
10.0
ns
Thld_9e
10.0
10.0
10.0
10.0
ns
MIIxTXD[3:0],
MIIxTXENP,
MIIxTXER
Tdo_9f
MIIxTXCLK
rising
0.0
25.0
0.0
25.0
0.0
25.0
0.0
25.0
ns
Table 9 Ethernet AC Timing Characteristics
Tpw_8n
Tpw_8n
Tpw_8n is the minimum amount of time before DMAREQN is
recognized as asserted or deasserted.
EXTCLK
DMAREQN
ICLK
CSN
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