參數(shù)資料
型號: 79RC32K438300BBI
廠商: Integrated Device Technology, Inc.
英文描述: IDTTM InterpriseTM Integrated Communications Processor
中文描述: IDTTM InterpriseTM集成通信處理器
文件頁數(shù): 35/59頁
文件大小: 644K
代理商: 79RC32K438300BBI
35 of 59
May 25, 2004
IDT 79RC32438
Signal
Symbol
Reference
Edge
200MHz
233MHz
266MHz
300MHz
Unit
Conditions
Timing
Diagram
Reference
Min
Max
Min
Max
Min
Max
Min
Max
EJTAG and JTAG
JTAG_TCK
Tper_16a
none
25.0
50.0
25.0
50.0
25.0
50.0
25.0
50.0
ns
See Figure 22.
Thigh_16a,
Tlow_16a
10.0
25.0
10.0
25.0
10.0
25.0
10.0
25.0
ns
JTAG_TMS
1
,
JTAG_TDI
1.
The JTAG specification, IEEE 1149.1, recommends that both JTAG_TMS and EJTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N changes from 0 to 1.
Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK when either JTAG_TMS or EJTAG_TMS is low, because the
TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state.
2.
The values for this symbol were determined by calculation, not by testing.
Tsu_16b
JTAG_TCK
rising
2.4
2.4
2.4
2.4
ns
Thld_16b
1.0
1.0
1.0
1.0
ns
JTAG_TDO
Tdo_16c
JTAG_TCK
falling
11.3
11.3
11.3
11.3
ns
Tdz_16c
2
11.3
11.3
11.3
11.3
ns
JTAG_TRST_N
Tpw_16d
2
none
25.0
25.0
25.0
25.0
ns
EJTAG_TMS
1
Tsu_16e
JTAG_TCK
rising
2.0
2.0
2.0
2.0
ns
Thld_6e
1.0
1.0
1.0
1.0
ns
VSENSE
Trise_16f
none
2
2
2
2
sec
Measured from
0.5V (T
active
)
See Figure 24.
Table 14 JTAG AC Timing Characteristics
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