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參數資料
| 型號： | 79RC32438 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | IDTTM InterpriseTM Integrated Communications Processor |
| 中文描述： | IDTTM InterpriseTM集成通信處理器 |
| 文件頁數： | 6/59頁 |
| 文件大小： | 644K |
| 代理商： | 79RC32438 |
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6 of 59
May 25, 2004
IDT 79RC32438
DDRVREF
I
DDR Voltage Reference.
SSTL_2 DDR voltage reference generated by an
external source.
DDRWEN
O
DDR Write Enable.
DDR write enable is asserted during DDR write transac-
tions.
PCI Bus
PCIAD[31:0]
I/O
PCI Multiplexed Address/Data Bus
. Address is driven by a bus master during
initial PCIFRAMEN assertion. Data is then driven by the bus master during
writes or by the bus target during reads.
PCICBEN[3:0]
I/O
PCI Multiplexed Command/Byte Enable Bus
. PCI command is driven by the
bus master during the initial PCIFRAMEN assertion. Byte enable signals are
driven by the bus master during subsequent data phase(s).
PCICLK
I
PCI Clock
. Clock used for all PCI bus transactions.
PCIDEVSELN
I/O
PCI Device Select
. This signal is driven by a bus target to indicate that the tar-
get has decoded the address as one of its own address spaces.
PCIFRAMEN
I/O
PCI Frame
. Driven by a bus master. Assertion indicates the beginning of a bus
transaction. Negation indicates the last data.
PCIGNTN[3:0]
I/O
PCI Bus Grant
.
In PCI host mode with internal arbiter:
The assertion of these signals indicates to the agent that the internal RC32438
arbiter has granted the agent access to the PCI bus.
In PCI host mode with external arbiter:
PCIGNTN[0]: asserted by an external arbiter to indicate to the RC32438 that
access to the PCI bus has been granted.
PCIGNTN[3:1]: unused and driven high.
In PCI satellite mode:
PCIGNTN[0]: This signal is asserted by an external arbiter to indicate to the
RC32438 that access to the PCI bus has been granted.
PCIGNTN[1]: this signal takes on the alternate function of PCIEECS and is used
as a PCI Serial EEPROM chip select
PCIGNTN[3:2]: unused and driven high.
Note
: When the GPIO register is programmed in the alternate function mode for
bits GPIO [26] and [28], these bits become PCIGNTN [4] and [5] respectively.
PCIIRDYN
I/O
PCI Initiator Ready
. Driven by the bus master to indicate that the current datum
can complete.
PCILOCKN
I/O
PCI Lock
. This signal is asserted by an external bus master to indicate that an
exclusive operation is occurring.
PCIPAR
I/O
PCI Parity
. Even parity of the PCIAD[31:0] bus. Driven by the bus master during
address and write Data phases. Driven by the bus target during the read data
phase.
PCIPERRN
I/O
PCI Parity Error
. If a parity error is detected, this signal is asserted by the
receiving bus agent 2 clocks after the data is received.
Signal
Type
Name/Description
Table 1 Pin Description (Part 3 of 9)
相關PDF資料 |
PDF描述 |
|---|---|
| 79RC32K438-200BB | IDTTM InterpriseTM Integrated Communications Processor |
| 79RC32K438-200BBI | IDTTM InterpriseTM Integrated Communications Processor |
| 79RC32K438-233BB | IDTTM InterpriseTM Integrated Communications Processor |
| 79RC32K438-233BBI | IDTTM InterpriseTM Integrated Communications Processor |
| 79RC32K438-266BB | IDTTM InterpriseTM Integrated Communications Processor |
相關代理商/技術參數 |
參數描述 |
|---|---|
| 79RC32438-200BB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| 79RC32438-200BBI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| 79RC32438-233BB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| 79RC32438-233BBI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| 79RC32H434-266BC | 功能描述:處理器 - 專門應用 RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數據總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數據緩存: 數據 RAM 大小:128 KB 數據 ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
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