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參數(shù)資料
| 型號： | 78Q8430-100IGTR/F |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 61/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LAN MEDIA ACCESS CTLR 100LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 控制器類型： | 以太網(wǎng)控制器，MAC/PHY |
| 電源電壓： | 3.3V |
| 電流 - 電源： | 230mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP（14x14） |
| 包裝： | 帶卷 (TR) |
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78Q8430 Data Sheet
DS_8430_001
64
Rev. 1.2
7.6.17 PROM Control Register
Name: PRCR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x14C
Bits
Type
Default
Description
31:9
X
0000
Reserved
8
RW
0
Busy
Writing a 1 initiates the EEPROM data transfer. The hardware will clear
the bit when the operation completes.
7:6
RW
0x0
Operation
1 1 = Erase.
1 0 = Read.
0 1 = Write.
0 0 = Enable or Disable Writing, as specified in PROM Addr:
[5:4] = 11, Enable
[5:4] = 00, Disable
5:0
RW
0x00
PROM Addr
Address of the EEPROM to access.
7.6.18 MAC Control Register
Name: MCR
Reset Val: 0x0080_0050
Block: CTL
Address: 0x154
Bits
Type
Default
Description
31:28
X
0000
Reserved
27
RW
0
Tx Enable
When this bit is clear transmitting stops immediately.
26
RW
0
Tx Halt
When this bit is set transmitting stops at the end of the current frame.
25
RW
0
Rx Enable
When this bit is clear receiving stops immediately.
24
RW
0
Rx Halt
When this bit is set receiving stops at the end of the current frame.
23
RW
1
Rx Drop Error
When this bit is set then an error in the first 256 bytes will cause a
packet to be dropped. If clear, error packets are forwarded to the host.
22
RW
0
Keep Dropped Status
Normally, the status for a dropped frame is not added to the receive
status FIFO. When this bit is set then a status for all frames, including
dropped frames, is added to the receive status FIFO. The status for a
dropped frame will have a size of zero in the RPSR.
21
RW
0
Jumbo OK
Normally frames in excess of the maximum allowed by 802.3 are
flagged as bad. If this bit is set then larger frame sizes are allowed.
20:18
0000
Reserved
17
RW
0
MACRST
Software re-initialization. Setting this bit will also automatically set both
Rx and Tx Halt bits and clear both Rx and Tx Enable bits. This bit is
only cleared by writing a zero.
16
RW
0
MACLOOP
Loopback mode for the MAC.
15:8
X
0x000
Reserved
7
RW
0
No Rx PAD
Strip the padding bytes from the end of received frames that are 64
bytes in length. When the padding is stripped from a frame the CRC is
stripped as well.
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