參數(shù)資料
型號(hào): 78Q8430-100IGTR/F
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 60/88頁(yè)
文件大?。?/td> 0K
描述: IC LAN MEDIA ACCESS CTLR 100LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1,000
控制器類型: 以太網(wǎng)控制器,MAC/PHY
電源電壓: 3.3V
電流 - 電源: 230mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-LQFP(14x14)
包裝: 帶卷 (TR)
DS_8430_001
78Q8430 Data Sheet
Rev. 1.2
63
7.6.13 BIST Bypass Mode Data Register
Name: BBDR
Reset Val: N/A
Block: CTL
Address: 0x13C
Bits
Type
Default
Description
31:0
R/W
RAM Data
Reads and writes to these bits go directly to the QMEM RAM at the
location indicated by BCR only when the BIST mode is set to BYPASS.
7.6.14 Station Management Data Register
Name: MDDAR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x140
Bits
Type
Default
Description
31:16
X
0000
Reserved
15:0
RW
0
SMI Data
Data read from or data to be written to the PHY. See Section 7.7.
7.6.15 Station Management Control and Address Register
Name: MDCAR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x144
Bits
Type
Default
Description
31:13
X
0000
Reserved
12
RW
0
Preamble
Writing a 1 suppresses the generation of the 32-bit PHY station
management preamble before the PHY register transfer. The internal
PHY of the 8430 does not require the preamble.
11
RW
0
Busy
Writing a 1 initiates the PHY register transfer. The hardware will clear
the bit when the operation completes.
10
RW
0
RegWr
Writing a 1 indicated the MDDAR data is to be written to the PHY.
Writing a 0 causes the PHY register to be read and the data placed in
the MDDAR .
9:5
RW
0
PHY Addr
Address of the PHY to access.
4:0
RW
0
PHY Reg
Address of the PHY register to access.
7.6.16 PROM Data Register
Name: PRDR
Reset Val: 0x0000_0000
Block: CTL
Address: 0x148
Bits
Type
Default
Description
31:16
X
0000
Reserved
15:0
RW
0000
PROM Data
Data to write to or read from the EEPROM device.
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