參數(shù)資料
型號: 784215A
廠商: NEC Corp.
英文描述: MOS INTEGRATED CIRCUIT
中文描述: 馬鞍山集成電路
文件頁數(shù): 13/100頁
文件大小: 564K
代理商: 784215A
Data Sheet U14121EJ2V0DS00
13
μ
PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY
www.DataSheet4U.com
4. BLOCK DIAGRAM
INTP2/NMI
INTP0, INTP1,
INTP3 to INTP6
Programmable
interrupt
controller
Real-time
output port
Timer/event
counter 7
(8 bits)
Timer/event
counter 6
(8 bits)
Timer/event
counter 5
(8 bits)
Timer/event
counter 2
(8 bits)
Timer/event
counter 1
(8 bits)
Timer/event
counter
(16 bits)
Watch timer
Timer/event
counter 8
(8 bits)
Watchdog timer
TI00
TI01
TO0
TI1
TO1
TI2
TO2
TI5/TO5
TI6/TO6
TI7/TO7
TI8/TO8
NMI/INTP2
RTP0 to RTP7
Clock output
control
A/D
converter
AV
DD
AV
SS
PCL
BUZ
AV
REF0
ANI0 to ANI7
D/A
converter
ANO0
ANO1
AV
SS
P03/INTP3
AV
REF1
78K/IV
CPU Core
ROM
RAM
Baud-rate
generator
RxD1/SI1
TxD1/SO1
ASCK1/SCK1
RxD2/SI2
TxD2/SO2
ASCK2/SCK2
SI0/SDA0
SO0
SCK0/SCL0
Bus I/F
UART/IOE1
RD
WR
WAIT
ASTB
EXA
Note 2
A0 to A7
AD0 to AD7
A8 to A15
A16 to A19
Port 1
P10 to P17
Port 0
P00 to P06
Port 2
P20 to P27
Port 3
P30 to P37
Port 4
P40 to P47
Port 5
P50 to P57
Port 6
P60 to P67
Port 7
P70 to P72
Port 8
P80 to P87
Port 9
P90 to P95
Port 10
P100 to P103
Port 12
P120 to P127
Port 13
P130, P131
Buzzer output
System control
RESET
XT2
X1
XT1
X2
V
SS
TEST
V
DD
Clocked
serial
interface
Note 1
Baud-rate
generator
UART/IOE2
Notes 1.
This function supports the I
products only.
2.
The EXA pin is available in
μ
PD784218A, 784218AY Subseries products only.
2
C bus interface and is available in
μ
PD784216AY/784218AY Subseries
Remark
The internal ROM and RAM capacities differ depending on the product.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
784215AY 制造商:NEC 制造商全稱:NEC 功能描述:MOS INTEGRATED CIRCUIT
784216A 制造商:NEC 制造商全稱:NEC 功能描述:MOS INTEGRATED CIRCUIT
784216AY 制造商:NEC 制造商全稱:NEC 功能描述:MOS INTEGRATED CIRCUIT
784217A 制造商:NEC 制造商全稱:NEC 功能描述:MOS INTEGRATED CIRCUIT
784217AY 制造商:NEC 制造商全稱:NEC 功能描述:MOS INTEGRATED CIRCUIT