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參數(shù)資料
| 型號(hào)： | 75HVD07 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | MS3420-12 |
| 中文描述： | 高輸出RS - 485收發(fā) |
| 文件頁(yè)數(shù)： | 8/19頁(yè) |
| 文件大?。?/td> | 220K |
| 代理商： | 75HVD07 |
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SN65HVD05, SN65HVD06, SN65HVD07
SN75HVD05, SN75HVD06, SN75HVD07
SLLS533B
–
MAY 2002
–
REVISED MAY 2003
www.ti.com
8
Input
Generator
50
3 V
VO
S1
1.5 V
1.5 V
tPLZ
2.3 V
0.5 V
≈
3 V
0 V
VOL
VI
VO
Generator: PRR = 100 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50
RL = 110
±
1%
CL = 50 pF
±
20%
CL Includes Fixture
and Instrumentation
Capacitance
D
A
B
DE
VI
tPZL(1 & 2)
VCC
VCC
Figure 6. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
VID
VA
VB
IO
A
B
IB
VO
R
IA
VIC
VA + VB
2
Figure 7. Receiver Voltage and Current Definitions
Input
Generator
50
Generator: PRR = 100 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50
VO
1.5 V
0 V
1.5 V
1.5 V
3 V
VOH
VOL
1.5 V
10%
1.5 V
10%
tPLH
tPHL
90%
tr
tf
90%
VI
VO
CL = 15 pF
±
20%
CL Includes Fixture
and Instrumentation
Capacitance
A
B
RE
VI
R
0 V
Figure 8. Receiver Switching Test Circuit and Voltage Waveforms
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