參數(shù)資料
型號(hào): 75HVD07
廠商: Texas Instruments, Inc.
英文描述: MS3420-12
中文描述: 高輸出RS - 485收發(fā)
文件頁數(shù): 6/19頁
文件大?。?/td> 220K
代理商: 75HVD07
SN65HVD05, SN65HVD06, SN65HVD07
SN75HVD05, SN75HVD06, SN75HVD07
SLLS533B
MAY 2002
REVISED MAY 2003
www.ti.com
6
RECEIVER SWITCHING CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
14.6
MAX
25
UNIT
ns
tPLH
tPHL
Propagation delay time, low-to-high-level output 1/2 UL
HVD05
Propagation delay time, high-to-low-level output 1/2 UL
HVD05
14.6
25
ns
tPLH
Propagationdelaytime low to high leveloutput1/8UL
Propagation delay time, low-to-high-level output 1/8 UL
HVD06
55
70
ns
HVD07
VID=
VID =
1.5 V to 1.5 V,
CL = 15 pF,
CL 15 F,
See Figure 8
55
70
tPHL
Propagationdelaytime high to low leveloutput1/8UL
Propagation delay time, high-to-low-level output 1/8 UL
HVD06
55
70
ns
HVD07
55
70
HVD05
2
tsk(p)
tsk( )
Pulse skew (|tPHL tPLH|)
HVD06
4.5
ns
HVD07
4.5
HVD05
6.5
tsk(pp)(2)
Part-to-part skew
Part to art skew
HVD06
14
ns
)( )
HVD07
14
tr
tf
tPZH1
tPZL1
tPHZ
tPLZ
tPZH2
tPZL2
(1)All typical values are at 25
°
C and with a 5-V supply.
(2)tsk(pp) is the magnitude of the difference n propagation delay times between any specified terminals of two devices when both devices operate
with the same supply voltages, at the same temperature, and have identical packages and test circuits.
Output signal rise time
CL = 15 pF,
CL = 15 F,
See Figure 8
2
3
ns
Output signal fall time
2
3
Output enable time to high level
10
Output enable time to low level
CL = 15 pF,
DE at 3 V,
See Figure 9
10
ns
Output disable time from high level
15
Output disable time from low level
15
Propagation delay time, standby-to-high-level output
CL = 15 pF
CL = 15 F
,
DE at 0,
See Figure 10
6
Propagation delay time, standby-to-low-level output
6
μ
s
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