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| 型號(hào)： | 7531GROUP |
| 英文描述： | 250MA CMOS LDO, ISUPPLY 1UA & 2% VOUT ACCURACY, -40C to +125C, 3-SOT-89, T/R |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁(yè)數(shù)： | 21/64頁(yè) |
| 文件大小： | 633K |
| 代理商： | 7531GROUP |
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7531 Group
MITSUBISHI MICROCOMPUTERS
21
Fig. 23 Block diagram of UART serial I/O
Fig. 24 Operation of UART serial I/O function
Serial I/O
G
Serial I/O1
Serial I/O1 can be used as an asynchronous (UART) serial I/O. A
dedicated timer (baud rate generator) is also provided for baud rate
generation when serial I/O1 is in operation.
Eight serial data transfer formats can be selected, and the transfer
formats to be used by a transmitter and a receiver must be identical.
Each of the transmit and receive shift registers has a buffer register
(the same address on memory). Since the shift register cannot be
written to or read from directly, transmit data is written to the transmit
buffer, and receive data is read from the respective buffer registers.
These buffer registers can also hold the next data to be transmitted
and receive 2-byte receive data in succession.
By selecting “1” for continuous transmit valid bit (bit 2 of SIO1CON),
continuous transmission of the same data is made possible.
This can be used as a simplified PWM.
OE
PE FE
1/16
X
IN
1/4
1/16
Data bus
Receive Buffer Register
Address
(0018
16
)
Receive Shift Register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
ST Detector
SP Detector
UART Control Register
Address (001B
16
)
Address (001A
16
)
Character length selection bit
7-bit
8-bit
Clock Control Circuit
Baud Rate Generator
Address (001C
16
)
Division ratio 1/(n+1)
BRG count source selection bit
Transmit Buffer Register
Data bus
Transmit Shift Register
Address
(0018
16
)
Transmit shift register shift
completion flag (TSC)
Transmit buffer empty flag (TBE)
Transmit interrupt request (TI)
Address (0019
16
)
Character length selection bit
Transmit interrupt source selection bit
Continuous transmit valid bit
Serial I/O1 control register
P1
0
/R
X
D
P1
1
/T
X
D
Serial I/O1 status register
ST/SP/PA Generator
TSC=0
TBE=1
RBF=0
TBE=0
TBE=0
RBF=1
RBF=1
ST
D
0
D
1
SP
D
0
D
1
ST
SP
TBE=1
TSC=1*
ST
D
0
D
1
SP
D
0
D
1
ST
SP
1 :
Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2 :
The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes “1”, depending on the setting of the transmit
interrupt source selection bit (TIC) of the serial I/O1 control register.
3 :
The receive interrupt (RI) is set when the RBF flag becomes “1”.
4 :
After data is written to the transmit buffer when TSC = 1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC = 0.
Notes
Transmit/Receive Clock
Transmit Buffer Register
Write Signal
Serial Output T
X
D
Receive Buffer Register
Read Signal
Serial Input R
X
D
* Generated at second bit in 2-stop -bit
mode
1 Start Bit
7 or 8 Data Bit
1 or 0 Parity Bit
1 or 2 Stop Bit
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