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參數(shù)資料
| 型號： | 7531GROUP |
| 英文描述： | 250MA CMOS LDO, ISUPPLY 1UA & 2% VOUT ACCURACY, -40C to +125C, 3-SOT-89, T/R |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 19/64頁 |
| 文件大?。?/td> | 633K |
| 代理商： | 7531GROUP |
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7531 Group
MITSUBISHI MICROCOMPUTERS
19
Timers
The 7531 Group has 3 timers: timer X, timer 1 and timer 2.
The division ratio of every timer and prescaler is 1/(n+1) provided
that the value of the timer latch or prescaler is n.
All the timers are down count timers. When a timer reaches “0”, an
underflow occurs at the next count pulse, and the corresponding timer
latch is reloaded into the timer. When a timer underflows, the inter-
rupt request bit corresponding to each timer is set to “1”.
G
Timer 1, Timer 2
Prescaler 12 always counts f(X
IN
)/16. Timer 1 and timer 2 always
count the prescaler output and periodically sets the interrupt request
bit.
G
Timer X
Timer X can be selected in one of 4 operating modes by setting the
timer X mode register.
Timer Mode
The timer counts the signal selected by the timer X count source
selection bit.
Pulse Output Mode
The timer counts the signal selected by the timer X count source
selection bit, and outputs a signal whose polarity is inverted each
time the timer value reaches “0”, from the CNTR
0
pin.
When the CNTR
0
active edge switch bit is “0”, the output of the
CNTR
0
pin is started with an “H” output.
At “1”, this output is started with an “L” output. When using a timer in
this mode, set the port P1
4
direction register to output mode.
Event Counter Mode
The operation in the event counter mode is the same as that in the
timer mode except that the timer counts the input signal from the
CNTR
0
pin.
When the CNTR
0
active edge switch bit is “0”, the timer counts
the rising edge of the CNTR
0
pin. When this bit is “1”, the timer
counts the falling edge of the CNTR
0
pin.
Pulse Width Measurement Mode
When the CNTR
0
active edge switch bit is “0”, the timer counts the
signal selected by the timer X count source selection bit while the
CNTR
0
pin is “H”. When this bit is “1”, the timer counts the signal
while the CNTR
0
pin is “L”.
In any mode, the timer count can be stopped by setting the timer X
count stop bit to “1”. Each time the timer overflows, the interrupt
request bit is set.
Fig. 20 Structure of timer X mode register
Fig. 21 Timer count source setting register
Timer X mode register
(TM : address 002B
16
, initial value: 00
16
)
Timer X operating mode bits
b1 b0
0 0 : Timer mode
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width measurement mode
CNTR
0
active edge switch bit
0 : Interrupt at falling edge
Count at rising edge
(in event counter mode)
1 : Interrupt at rising edge
Count at falling edge
(in event counter mode)
Timer X count stop bit
0 : Count start
1 : Count stop
Not used (return “0” when read)
b7 b0
Timer count source set register
(TCSS : address 002E
16
, initial value: 00
16
)
Timer X count source selection bit (Note)
0 : f(X
IN
)/16
1 : f(X
IN
)/2
b7 b0
Not used (return “0” when read)
Note :
To switch the timer X count source selection bit ,
stop the timer X count operation.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
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