參數(shù)資料
型號(hào)： 7510
英文描述： 7510 Group Datasheet Datasheet 469K/JAN.10.98
中文描述： 7510組數(shù)據(jù)表數(shù)據(jù)表469K/JAN.10.98
文件頁(yè)數(shù)： 20/44頁(yè)
文件大?。?/td> 469K
代理商： 7510
19
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O mode selection bit of the serial I/O control
register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer,
but the two buffers have the same address in memory.
Since the shift register cannot be written to or read from directly,
transmit data is written to the transmit buffer, and receive data is
read from the receive buffer. The transmit buffer can also hold the
next data to be transmitted, and the receive buffer can hold a char-
acter while the next character is being received.
Fig. 15 Block diagram of UART serial I/O
Fig. 16 Operation of UART serial I/O function
Data bus
Receive buffer
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Serial I/O control register
Receive shift register
Clock control circuit
P4
4
/R
X
D
1
P3
0
/R
X
D
2
Address 001A
16
0032
16
Address
0018
16
0030
16
UART control register
Address 001B
16
0033
16
SP detector
PE FE
7 bits
8 bits
Character length selection bit
OE
P4
6
/S
CLK1
P3
2
/S
CLK2
f(X
IN
)
P4
5
/T
X
D
1
P3
1
/T
X
D
2
Baud rate generator
Address 001C
16
0034
16
1/4
BRG count source selection bit
Frequency division ratio 1/(n+1)
1/16
Serial I/O synchronous clock selection bit
Character length selection bit
Transmit shift register
Transmit buffer register
Transmit interrupt source selection bit
Transmit interrupt request (TI)
Transmit shift completion flag (TSC)
Serial I/O status register
Address
0018
16
0030
16
Data bus
Contents in are for serial I/O2.
Transmit buffer empty flag (TBE)
Address 0019
16
0031
16
1/16
ST detector
ST/SP/PA generator
D
0
D
1
TBE = 1
SP
ST
D
0
D
1
ST
SP
TSC = 1
8
TBE = 0
TBE = 0
TSC = 0
TBE = 1
1 start bit
7 or 8 data bits
1 or 0 parity bit
1 or 2 stop bit(s)
8
Generated at 2nd bit in 2-stop-bit mode
RBF = 0
D
0
D
1
RBF = 1
SP
ST
D
0
D
1
ST
SP
RBF = 1
Transmit or receive clock
Transmit buffer write signal
Serial output T
X
D
Receive buffer read signal
Serial input R
X
D
Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes “1”, depending on the setting of the transmit
interrupt source selection bit (TIC) of the serial I/O control register.
The receive interrupt (RI) is set when the RBF flag becomes “1”.
After data is written to the transmit buffer when TSC = 1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC = 0.
Notes 1 :
2 :
3 :
4 :
相關(guān)PDF資料
PDF描述
7513 7513 Group Datasheet Datasheet 1067K/FEB.06.01
75160-101-36 STIFTLEISTE ABTRENNBAR 1REIHIG 36POL
75160-102-36 STIFTLEISTE ABTRENNBAR 1REIHIG 36POL
75160-105-36 STIFTLEISTE ABTRENNBAR 1REIHIG 36POL
75160-301-36 STIFTLEISTE ABTRENNBAR 1REIHIG 36POL
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