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參數(shù)資料
| 型號(hào)： | 7510 |
| 英文描述： | 7510 Group Datasheet Datasheet 469K/JAN.10.98 |
| 中文描述： | 7510組數(shù)據(jù)表數(shù)據(jù)表469K/JAN.10.98 |
| 文件頁數(shù)： | 10/44頁 |
| 文件大小： | 469K |
| 代理商： | 7510 |
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9
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Timer X function I/O
Timer Y function I/O
Port P5
Common
Segment
P0
0
–P0
7
P1
0
–P1
7
P2
0
–P2
7
I/O PORTS
Direction Registers
The 7510 group has 41 programmable I/O pins arranged in six I/O
ports (ports P0 to P5). The I/O ports have direction registers which
determine the input/output direction of each individual pin. Each
bit in a direction register corresponds to one pin, each pin can be
set to be input or output.
When “0” is written to the bit corresponding to a pin, that pin be-
comes an input pin. When “1” is written to that bit, that pin
becomes an output pin.
If data is read from a pin which is set for output, the value of the
port output latch is read, not the value of the pin itself. Pins set to
input are floating and can read the value of the pin itself. If a pin
set to input is written to, only the port output latch is written to and
the pin remains floating.
Port Pull-up Control Registers
The 7510 group is equipped with internal pull-ups that can be en-
abled by software. Each I/O port of ports P0–P5 has an port Pi (i=
0 to 5) pull-up control register (addresses 000C
16
to 0011
16
). Each
bit of the pull-up control register controls a corresponding bit of the
port. The value written to each individual bit determines whether
the pull-up of the corresponding pin is either enabled or disabled.
When “0” is written to the pull-up control register, the pull up on the
pin is disabled. When “1” is written to the pull-up control register,
the pull-up on the pin is enabled.
After reset, all the pull-up control registers are initialized to “00
16
”,
disabling all the internal pull-ups.
Fig. 4 Structure of port Pi pull-up control register
Pin
Name
Input/Output
Input/output,
individual bits
Input/output,
individual bits
Input/output,
individual bits
I/O Format
Port P0
Port P1
Port P2
Non-Port Function
Related SFRs
Port P3
Port P4
Input/output,
individual bits
Input
Input/output,
individual bits
Input/output,
individual bits
Output
Output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible input level
CMOS compatible
input level
CMOS 3-state output
CMOS compatible input level
CMOS 3-state output
LCD common output
LCD segment output
Key-on wake up
interrupt input
Serial I/O2
function I/O
External interrupt
input
Serial I/O1
function I/O
Sub-clock generat-
ing circuit I/O
P3
0
/R
X
D
2
,
P3
1
/T
X
D
2
,
P3
2
/ S
CLK2
,
P3
3
/S
RDY2
P3
4
–P3
7
P4
0
/INT
0
P4
1
/INT
1
P4
2
/CNTR
0
,
P4
3
/CNTR
1
P4
4
/R
X
D
1
,
P4
5
/T
X
D
1
,
P4
6
/ S
CLK1
,
P4
7
/S
RDY1
P5
0
/X
COUT
,
P5
1
/X
CIN
COM
0
–
COM
15
SEG
0
–
SEG
79
Notes 1:
For details of how to use double-function ports as function I/O ports, refer to the applicable sections.
2:
Make sure that the input level at each pin is either 0 V or V
CC
during execution of the STP instruction.
When an input level is at an intermediate potential, a current will flow from V
CC
to V
SS
through the input-stage gate.
CPU mode register
LCD mode register
Interrupt control
register 2
Serial I/O2 control
register
Serial I/O2 status register
UART control register 2
Timer X mode register
Timer Y mode register
Serial I/O1 control
register
Serial I/O1 status register
UART1 control register
Ref. No.
(1)
(1)
(2)
(3)
(4)
(5)
(6)
(1)
(7)
(8)
(9)
(8)
(3)
(4)
(5)
(6)
(1)
CMOS compatible input level
CMOS 3-state output
CMOS compatible input level
CMOS 3-state output
CMOS compatible input level
CMOS 3-state output
b7
Port Pi pull-up control register
(PULLPi : addresses 000C
16
to 0011
16
)
Pi
0
pull-up
Pi
1
pull-up
Pi
2
pull-up
Pi
3
pull-up
Pi
4
pull-up
Pi
5
pull-up
Pi
6
pull-up
Pi
7
pull-up
b0
0 : Disabled
1 : Enabled
i = 0 to 5
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