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| 型號(hào)： | 7510 |
| 英文描述： | 7510 Group Datasheet Datasheet 469K/JAN.10.98 |
| 中文描述： | 7510組數(shù)據(jù)表數(shù)據(jù)表469K/JAN.10.98 |
| 文件頁數(shù)： | 13/44頁 |
| 文件大?。?/td> | 469K |
| 代理商： | 7510 |
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12
7510 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Interrupt request
generating conditions
High
FFFD
16
INTERRUPTS
A total of 15 sources can generate interrupts: 5 external, 9 inter-
nal, and 1 software.
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software in-
terrupt set by the BRK instruction. An interrupt is generated if the
corresponding interrupt request and enable bits are “1” and the in-
terrupt disable flag is “0”.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The reset and BRK instruction can not be disabled with any flag or
bit.
The I flag disables all interrupts except for the BRK instruction in-
terrupt and the reset.
When several interrupts occur at the same time, the interrupts are
received according to priority.
Interrupt Operation
When an interrupt is received, the program counter and processor
status register are automatically pushed onto the stack. The inter-
rupt disable flag is set to inhibit other interrupts from interfering.
The corresponding interrupt request bit is cleared and the interrupt
jump destination address is read from the vector table into the pro-
gram counter.
Notes on Use
When the active edge of an external interrupt (INT
0
, INT
1
, CNTR
0
,
or CNTR
1
) is changed, the corresponding interrupt request bit
may also be set. Therefore, please take following sequence;
(1) Disable the external interrupt which is selected.
(2) Change the active edge selection.
(3) Clear interrupt request which is selected to “0”.
(4) Enable the external interrupt which is selected.
Table 1 Interrupt vector addresses and priority
Interrupt source
Priority
Low
FFFC
16
Remarks
Reset (Note 2)
INT
0
INT
1
Non-maskable
External interrupt (active edge
selectable)
External interrupt (active edge
selectable)
Valid when serial I/O1 is se-
lected
Valid when serial I/O1 is se-
lected
Valid when serial I/O2 is se-
lected
Valid when serial I/O2 is se-
lected
External interrupt (active edge
selectable)
External interrupt (active edge
selectable)
External interrupt (valid when
an “L” level is applied)
Non-maskable software inter-
rupt
At BRK instruction execution
FFFA
16
FFF8
16
FFF6
16
FFF4
16
FFF2
16
FFF0
16
FFEE
16
FFEC
16
FFEA
16
FFE8
16
FFE6
16
FFE4
16
FFE2
16
FFE0
16
FFDC
16
FFFB
16
FFF9
16
FFF7
16
FFF5
16
FFF3
16
FFF1
16
FFEF
16
FFED
16
FFEB
16
FFE9
16
FFE7
16
FFE5
16
FFE3
16
FFE1
16
FFDD
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Serial I/O1
reception
Serial I/O1
transmission
Timer X
Timer Y
Timer 2
Timer 3
Serial I/O2
reception
Serial I/O2
transmission
CNTR
0
CNTR
1
Timer 1
Key-on wake up
BRK instruction
Notes 1:
Vector addresses contain interrupt jump destination addresses.
2:
Reset function in the same way as an interrupt with the highest priority.
Vector addresses (Note 1)
At reset
At detection of either rising or
falling edge of INT
0
input
At detection of either rising or
falling edge of INT
1
input
At end of serial I/O1 data re-
ception
At end of serial I/O1 transfer
shift or when transmission
buffer is empty
At timer X underflow
At timer Y underflow
At timer 2 underflow
At timer 3 underflow
At end of serial I/O2 data re-
ception
At end of serial I/O2 transfer
shift or when transmission
buffer is empty
At detection of either rising or
falling edge of CNTR
0
input
At detection of either rising or
falling edge of CNTR
1
input
At timer 1 underflow
At falling of conjunction of in-
put logic level for port P2 (at
input)
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