參數(shù)資料
型號： 74LVC1G125
廠商： Texas Instruments, Inc.
英文描述： 8-Bit Addressable Latches 16-SO -40 to 85
中文描述： 單總線緩沖器門具有三態(tài)輸出
文件頁數(shù)： 9/17頁
文件大?。?/td> 91K
代理商： 74LVC1G125
9397 750 13762
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 18 October 2004
9 of 17
Philips Semiconductors
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
[1]
All typical values are measured at T
amb
= 25
°
C.
These typical values are measured at V
CC
= 3.3 V.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = number of inputs switching;
Σ
(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
The condition is V
I
= GND to V
CC
.
[2]
[3]
[4]
t
rem
removal time master reset
see
Figure 7
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V
V
CC
= 3.0 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
see
Figure 6
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V
V
CC
= 3.0 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
see
Figure 6
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V
V
CC
= 3.0 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
see
Figure 6
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V
V
CC
= 3.0 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
1.9
1.4
1.3
1.2
1.0
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
t
su
set-up time D to CP
2.9
1.7
1.7
1.3
1.1
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
t
h
hold time D to CP
0.0
0.3
0.5
1.2
0.5
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
f
max
maximum clock pulse
frequency
80
175
175
175
200
-
-
-
-
-
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
Table 8:
GND = 0 V; see
Figure 8
Symbol
Dynamic characteristics
…continued
Parameter
Conditions
Min
Typ
Max
Unit
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