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參數(shù)資料
| 型號： | 74LVC1G80GW |
| 廠商： | Panasonic Corporation |
| 元件分類： | 通用總線功能 |
| 英文描述： | MS (MIL-C-5015)/97 SERIES 3106A SOLID-SHELL STRAIGHT PLUGS, STRAIGHT BODY STYLE, SOLDER TERMINATION, 20 SHELL SIZE, 20-15 INSERT ARRANGEMENT, PLUG GENDER, 7 CONTACTS |
| 中文描述： | MS(MIL - C - 5015)/ 97系列3106A固體殼直插頭，直插型，焊接，20個(gè)引腳，20—15插入排列，插頭類，7觸點(diǎn) |
| 文件頁數(shù)： | 1/17頁 |
| 文件大?。?/td> | 91K |
| 代理商： | 74LVC1G80GW |
1.
General description
The 74LVC1G175 is a high-performance, low-voltage, Si-gate CMOS device, superior
to most advanced CMOS compatible TTL families.
The input can be driven from either 3.3 Vor 5 V devices. This feature allows the use of
this device in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using I
off
. The I
off
circuitry
disables the output, preventing the damaging backflow current through the device when
it is powered down.
The 74LVC1G175 is a single positive edge triggered D-type flip-flop with individual
data (D) input, clock (CP) input, master reset (MR) input, and Q output.
The master reset (MR) is an asynchronous active LOW input and operate independently
of the clock input. Information on the data input is transferred to the Q output on the
LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time
prior to the LOW-to-HIGH clock transition, for predictable operation.
Schmitt-trigger action at all inputs makes the circuit highly tolerant to slower input rise and
fall times.
2.
Features
I
Wide supply voltage range from 1.65 V to 5.5 V
I
5 V tolerant inputs for interfacing with 5 V logic
I
High noise immunity
I
Complies with JEDEC standard:
N
JESD8-7 (1.65 V to 1.95 V)
N
JESD8-5 (2.3 V to 2.7 V)
N
JESD8B/JESD36 (2.7 V to 3.6 V).
I
±
24 mA output drive (V
CC
= 3.0 V)
I
ESD protection:
N
HBM EIA/JESD22-A114-B exceeds 2000 V
N
MM EIA/JESD22-A115-A exceeds 200 V.
I
CMOS low power consumption
I
Latch-up performance exceeds 250 mA
I
Direct interface with TTL levels
I
Inputs accept voltages up to 5 V
I
Multiple package options
I
Specified from
40
°
C to +85
°
C and
40
°
C to +125
°
C.
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
Rev. 01 — 18 October 2004
Product data sheet
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74LVC1G80GV | Single D-type flip-flop; positive-edge trigger |
| 74LVC1G80GM | Single D-type flip-flop; positive-edge trigger |
| 74LVC1G80 | Single D-type flip-flop; positive-edge trigger |
| 74LVC1G32GW | Single 2-input OR gate |
| 74LVC1G32GV | Single 2-input OR gate |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74LVC1G80GW,125 | 功能描述:觸發(fā)器 3.3V PICOGATE D-TYPE RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74LVC1G80GW,165 | 功能描述:觸發(fā)器 SINGLE D-TYPE RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74LVC1G80GW-G | 功能描述:觸發(fā)器 3.3V PICOGATE D-TYPE RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74LVC1G80GW-Q100,1 | 制造商:NXP Semiconductors 功能描述:74LVC1G80GW-Q100/UMT5/REELR// - Tape and Reel 制造商:NXP Semiconductors 功能描述:IC D-TYPE POS TRG SNGL 5TSSOP |
| 74LVC1G80GW-Q100,125 | 制造商:NXP Semiconductors 功能描述: |
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