參數(shù)資料
型號(hào)： 74LVC1G125
廠商： Texas Instruments, Inc.
英文描述： 8-Bit Addressable Latches 16-SO -40 to 85
中文描述： 單總線緩沖器門具有三態(tài)輸出
文件頁(yè)數(shù)： 7/17頁(yè)
文件大小： 91K
代理商： 74LVC1G125
9397 750 13762
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 18 October 2004
7 of 17
Philips Semiconductors
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
11. Dynamic characteristics
Table 8:
GND = 0 V; see
Figure 8
Symbol
T
amb
=
40
°
C to +85
°
C
[1]
t
PHL
, t
PLH
propagation delay CP to Q
Dynamic characteristics
Parameter
Conditions
Min
Typ
Max
Unit
see
Figure 6
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V
V
CC
= 3.0 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
see
Figure 7
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V
V
CC
= 3.0 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
see
Figure 6
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V
V
CC
= 3.0 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
see
Figure 7
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V
V
CC
= 3.0 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
see
Figure 7
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V
V
CC
= 3.0 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
see
Figure 6
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V
V
CC
= 3.0 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
1.5
1.0
1.0
4.9
3.1
3.2
3.1
2.2
13.4
7.1
7.1
5.7
4.0
ns
ns
ns
ns
ns
[2]
1.0
1.0
propagation delay MR to Q
1.5
1.0
1.0
4.3
2.8
3.0
2.5
2.0
12.9
7.0
7.0
5.8
4.1
ns
ns
ns
ns
ns
[2]
1.0
1.0
t
W
clock pulse width HIGH or
LOW
6.2
2.7
2.7
-
-
-
1.3
-
-
-
-
-
-
ns
ns
ns
ns
ns
[2]
2.7
2.0
master reset pulse width
LOW
6.2
2.7
2.7
-
-
-
1.6
-
-
-
-
-
-
ns
ns
ns
ns
ns
[2]
2.7
2.0
t
rem
removal time master reset
1.9
1.4
1.3
-
-
-
0.4
-
-
-
-
-
-
ns
ns
ns
ns
ns
[2]
1.2
1.0
t
su
set-up time D to CP
2.9
1.7
1.7
-
-
-
0.5
-
-
-
-
-
-
ns
ns
ns
ns
ns
[2]
1.3
1.1
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