參數(shù)資料
型號(hào): 74HCT40105PW
廠商: NXP SEMICONDUCTORS
元件分類: FIFO
英文描述: 8-Bit Parallel-Load Shift Registers 16-SO -40 to 85
中文描述: 16 X 4 OTHER FIFO, 120 ns, PDSO16
封裝: 4.40 MM, PLASTIC, MO-153, SOT-403-1, TSSOP-16
文件頁(yè)數(shù): 9/25頁(yè)
文件大小: 200K
代理商: 74HCT40105PW
1998 Jan 23
9
Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
74HC/HCT40105
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”
Output capability: standard
I
CC
category: MSI
Note to HCT types
The value of additional quiescent supply current (
I
CC
) for a unit load of 1 is given in the family specifications.
To determine
I
CC
per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
f
= t
f
= 6 ns; C
L
= 50 pF
INPUT
UNIT LOAD COEFFICIENT
OE
SI
D
n
MR
SO
0.75
0.40
0.30
1.50
0.40
SYMBOL PARAMETER
T
amb
(
°
C)
UNIT
TEST CONDITIONS
74HCT
V
CC
(V)
WAVEFORMS
+
25
40 to
+
85
40 to
+
125
min. typ.
max.
min.
max.
min.
max.
t
PHL
/ t
PLH
propagation delay
MR to DIR, DOR
propagation delay
SI to DIR
propagation delay
SO to DOR
propagation delay
SO to Q
n
propagation delay/
ripple through delay
SI to DOR
propagation delay/
bubble-up delay
SO to DIR
3-state output enable time
OE to Q
n
3-state output disable
time
OE to Q
n
output transition time
18
35
44
53
ns
4.5
Fig.8
t
PHL
21
42
53
63
ns
4.5
Fig.6
t
PHL
20
42
53
63
ns
4.5
Fig.9
t
PHL
/ t
PLH
40
80
100
120
ns
4.5
Fig.14
t
PLH
188
400
500
600
ns
4.5
Fig.10
t
PLH
244
500
625
750
ns
4.5
Fig.7
t
PZH
/ t
PZL
18
35
44
53
ns
4.5
Fig.16
t
PHZ
/ t
PLZ
15
30
38
45
ns
4.5
Fig.16
t
THL
/ t
TLH
7
15
19
22
ns
4.5
Fig.14
相關(guān)PDF資料
PDF描述
74HC40105 4-bit x 16-word FIFO register
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