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參數(shù)資料
| 型號： | 74HCT40105PW |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | FIFO |
| 英文描述： | 8-Bit Parallel-Load Shift Registers 16-SO -40 to 85 |
| 中文描述： | 16 X 4 OTHER FIFO, 120 ns, PDSO16 |
| 封裝： | 4.40 MM, PLASTIC, MO-153, SOT-403-1, TSSOP-16 |
| 文件頁數(shù)： | 17/25頁 |
| 文件大?。?/td> | 200K |
| 代理商： | 74HCT40105PW |
1998 Jan 23
17
Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
74HC/HCT40105
Expanded format
Fig.19 shows two cascaded FIFOs providing a capacity of 32 words
×
4 bits
Fig.20 shows the signals on the nodes of both FIFOs after the application of a SI pulse, when both FIFOs are initially
empty. After a rippled through delay, date arrives at the output of FIFO
A
. Due to SO
A
being HIGH, a DOR pulse is
generated. The requirements of SI
B
and D
nB
are satisfied by the DOR
A
pulse width and the timing between the rising
edge of DOR
A
and Q
nA
. After a second ripple through delay, data arrives at the output of FIFO
B
.
Fig.21 shows the signals on the nodes of both FIFOs after the application of a SO
R
pulse, when both FIFOs are initially
full. After a bubble-up delay a DIR
R
pulse is generated, which acts as a SO
A
pulse for FIFO
A
. One word is transferred
from the output of FIFO
A
to the input of FIFO
B
. The requirements of the SO
A
pulse for FIFO
A
is satisfied by the pulse
width of DOR
B
. After a second bubble-up delay an empty space arrives at D
nA
, at which time DIR
A
goes HIGH.
Fig.22 shows the waveforms at all external nodes of both FIFOs during a complete shift-in and shift-out sequence.
Fig.19 Cascading for increased word capacity; 32 words
×
4 bits.
The PC7HC/HCT40105 is easily cascaded to increase word capacity without any external circuitry. In cascaded format, all necessary
communications are handled by the FIFOs. Figs 17 and 19 demonstrate the intercommunication timing between FIFO
A
and FIFO
B
. Fig.22 gives an
overview of pulse and timing of two cascaded FIFOs, when shifted full and shifted empty again.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74HC40105 | 4-bit x 16-word FIFO register |
| 74HCT4015 | 8-Bit Parallel-Load Shift Registers 16-SO -40 to 85 |
| 74HC4015 | Dual 4-bit serial-in/parallel-out shift register |
| 74HCT4016 | Quad bilateral switches(四雙向開關(guān)) |
| 74HC4016 | Quad bilateral switches |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74HCT4015D | 功能描述:計數(shù)器移位寄存器 DUAL 4-BIT SHIFT REGISTER RoHS:否 制造商:Texas Instruments 計數(shù)器類型: 計數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| 74HCT4015D,112 | 功能描述:計數(shù)器移位寄存器 DUAL 4-BIT SHIFT RoHS:否 制造商:Texas Instruments 計數(shù)器類型: 計數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| 74HCT4015D,118 | 功能描述:計數(shù)器移位寄存器 DUAL 4-BIT SHIFT RoHS:否 制造商:Texas Instruments 計數(shù)器類型: 計數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| 74HCT4015D-T | 功能描述:計數(shù)器移位寄存器 DUAL 4-BIT SHIFT REGISTER RoHS:否 制造商:Texas Instruments 計數(shù)器類型: 計數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| 74HCT4015N | 功能描述:計數(shù)器移位寄存器 DUAL 4-BIT SHIFT REGISTER RoHS:否 制造商:Texas Instruments 計數(shù)器類型: 計數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
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