參數(shù)資料
型號: 74HCT40105PW
廠商: NXP SEMICONDUCTORS
元件分類: FIFO
英文描述: 8-Bit Parallel-Load Shift Registers 16-SO -40 to 85
中文描述: 16 X 4 OTHER FIFO, 120 ns, PDSO16
封裝: 4.40 MM, PLASTIC, MO-153, SOT-403-1, TSSOP-16
文件頁數(shù): 14/25頁
文件大?。?/td> 200K
代理商: 74HCT40105PW
1998 Jan 23
14
Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
74HC/HCT40105
Shift-out operation; high-speed burst mode
Fig.12 Waveforms showing SO minimum pulse width and maximum pulse frequency, in high-speed shift-out
burst mode.
In the high-speed mode, the burst-out rate is determined by the
minimum shift-out HIGH and shift-out LOW specifications. The
DOR flag is a don’t care condition and a SO pulse can be applied
without regard to the flag.
(1) HC : V
M
= 50%; V
I
= GND to V
.
HCT : V
M
= 1.3 V; V
I
= GND to 3 V.
Fig.13 Waveforms showing hold and set up times for D
n
input to SI input.
The shaded areas indicate when the input is permitted
to change for predictable output performance.
(1) HC : V
M
= 50%; V
I
= GND to V
.
HCT : V
M
= 1.3 V; V
I
= GND to 3 V.
Fig.14 Waveforms showing SO input to Q
n
output propagation delays and output transition time.
(1) HC : V
M
= 50%; V
I
= GND to V
.
HCT : V
M
= 1.3 V; V
I
= GND to 3 V.
相關PDF資料
PDF描述
74HC40105 4-bit x 16-word FIFO register
74HCT4015 8-Bit Parallel-Load Shift Registers 16-SO -40 to 85
74HC4015 Dual 4-bit serial-in/parallel-out shift register
74HCT4016 Quad bilateral switches(四雙向開關)
74HC4016 Quad bilateral switches
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