參數(shù)資料
型號(hào)： 74HCT40105PW
廠商： NXP SEMICONDUCTORS
元件分類： FIFO
英文描述： 8-Bit Parallel-Load Shift Registers 16-SO -40 to 85
中文描述： 16 X 4 OTHER FIFO, 120 ns, PDSO16
封裝： 4.40 MM, PLASTIC, MO-153, SOT-403-1, TSSOP-16
文件頁(yè)數(shù)： 18/25頁(yè)
文件大?。?/td> 200K
代理商： 74HCT40105PW
1998 Jan 23
18
Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
74HC/HCT40105
Fig.20 FIFO to FIFO communication; input timing under
empty condition.
(1) HC : V
M
= 50%; V
I
= GND to V
.
HCT : V
M
= 1.3 V; V
I
= GND to 3 V.
Notes to
Fig.20
1.
FIFO
A
and FIFO
B
initially empty, SO
A
held
HIGH in anticipation of data.
Load one word into FIFO
A
; SI pulse applied,
results in DIR pulse.
Data out
A
/data in
B
transition; valid data
arrives at FIFO
A
output stage after a specified
delay of the DOR flag, meeting data input
set-up requirements of FIFO
B
.
DOR
A
and SI
B
pulse HIGH; (ripple through
delay after SI
A
LOW) data is unloaded from
FIFO
A
as a result of the data output ready
pulse, data is shifted into FIFO
B
.
DIR
B
and SO
A
go LOW; flag indicates input
stage of FIFO
B
is busy, shift-out of FIFO
A
is
complete.
DIR
B
and SO
A
go HIGH automatically; the
input stage of FIFO
B
is again able to receive
data, SO is held HIGH in anticipation of
additional data.
DOR
B
goes HIGH; (ripple through delay after
SI
B
LOW) valid data is present one
propagation delay later at the FIFO
B
output
stage.
2.
3.
4.
5.
6.
7.
(1) HC : V
M
= 50%; V
I
= GND to V
.
HCT : V
M
= 1.3 V; V
I
= GND to 3 V.
Fig.21 FIFO to FIFO communication; output timing under
full condition.
Notes to
Fig.21
1.
FIFO
A
and FIFO
B
initially empty, SI
B
held
HIGH in anticipation of shifting in new data as
empty location bubbles-up.
Unload one word into FIFO
B
; SO pulse
applied, results in DOR pulse.
DIR
B
and SO
A
pulse HIGH; (bubble-up delay
after SO
B
LOW) data is loaded into FIFO
B
as
a result of the DIR pulse, data is shifted out of
FIFO
A
.
DOR
A
and SI
B
go LOW; flag indicates the
output stage of FIFO
A
is busy, shift-in to
FIFO
R
is complete.
DOR
A
and SI
B
go HIGH; flag indicates valid
data is again available at FIFO
A
output stage,
SI
B
is held HIGH, awaiting bubble-up of
empty location.
DIR
A
goes HIGH; (bubble-up delay after
SO
A
LOW) an empty location is present at
input stage of FIFO
A
.
2.
3.
4.
5.
6.
相關(guān)PDF資料
PDF描述
74HC40105 4-bit x 16-word FIFO register
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