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參數(shù)資料
| 型號： | 74ETL16245 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 16-Bit Data Transceiver with Incident Wave Switching |
| 中文描述： | 16位數(shù)據(jù)收發(fā)器事件波開關(guān) |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 190K |
| 代理商： | 74ETL16245 |
DC Electrical Characteristics
(Continued)
Symbol
Parameter
ETL16245
Units
V
CC
Conditions
Min
Typ
Max
I
CCH
Power Supply Current
40
mA
Max
All Outputs HIGH,
OE
e
LOW, DIR
e
HIGH or LOW
I
CCL
Power Supply Current
80
mA
Max
All Outputs LOW,
OE
e
LOW, DIR
e
HIGH or LOW
I
CCZ
Power Supply Current
OE
e
HIGH
All Others at V
CC
or GND
DIR
e
HIGH or LOW
40
mA
Max
I
CCD
Dynamic I
CC
No Load
(Note 1)
0.15
MHz
mA/
Max
Outputs Open
OE
n
e
GND, DIR
e
HIGH
One Bit Toggling, 50% Duty Cycle
V
OLP
Quiet Output Maximum
Dynamic V
OL
1.0
V
5.0
T
A
e
25
§
C (Note 2)
C
L
e
50 pF; R
L
e
500
X
T
A
e
25
§
C (Note 2)
C
L
e
50 pF; R
L
e
500
X
T
A
e
25
§
C (Note 4)
C
L
e
50 pF; R
L
e
500
X
T
A
e
25
§
C (Note 3)
C
L
e
50 pF; R
L
e
500
X
T
A
e
25
§
C (Note 3)
C
L
e
50 pF; R
L
e
500
X
V
OLV
Quiet Output Minimum
Dynamic V
OL
b
1.4
V
5.0
V
OHV
Minimum High Level Dynamic
Output Voltage (Note 1)
2.7
V
5.0
V
IHD
Minimum High Level Dynamic
Input Voltage (Note 1)
2.0
1.5
V
5.0
V
ILD
Maximum Low Level Dynamic
Input Voltage (Note 1)
1.2
0.8
V
5.0
Note 1:
Guaranteed, but not tested.
Note 2:
Max. number of outputs defined as (n). n
b
1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested.
Note 3:
Max. number of data inputs (n) switching. n
b
1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (V
ILD
), 0V to threshold (V
IHD
).
Guaranteed, but not tested.
Note 4:
Max. number of outputs defined as (n). n
b
1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.
AC Electrical Characteristics
Symbol
Parameter
74ETL
54ETL
74ETL
Units
Fig.
No.
T
A
e a
25
§
C
V
CC
e a
5V
T
A
e b
55
§
C to
a
125
§
C
V
CC
e
4.5V–5.5V
T
A
e b
40
§
C to
a
85
§
C
V
CC
e
4.5V–5.5V
Min
Typ
Max
Min
Max
Min
Max
t
PLH
t
PHL
Propagation
Delay A
n
to B
n
1.5
1.5
7.0
7.0
1.5
1.5
7.0
7.0
ns
1, 2, 4
t
PLH
t
PHL
Propagation
Delay B
n
to A
n
1.5
1.5
7.0
7.0
1.5
1.5
7.0
7.0
ns
1, 2, 4
t
PZH
t
PZL
Output Enable
Time
1.0
1.0
7.0
7.0
1.0
1.0
7.0
7.0
ns
1, 2, 3
t
PHZ
t
PLZ
Output Disable
Time
Rise Time 1V
x
2V,
A
n
Outputs
Fall Time 2V
x
1V,
A
n
Outputs
1.0
1.0
7.0
7.0
1.0
1.0
7.0
7.0
ns
1, 2, 3
t
r
1.2
3.0
1.2
3.0
ns
1, 2, 4
t
f
1.2
3.0
1.2
3.0
ns
1, 2, 4
6
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