參數(shù)資料
型號: 73M1866B-IM/F
廠商: Maxim Integrated Products
文件頁數(shù): 7/88頁
文件大小: 0K
描述: MICRODAA SGL PCM HIGHWAY 42-QFN
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 260
系列: MicroDAA™
功能: 數(shù)據(jù)存取裝置(DAA)
接口: PCM,串行,SPI
電路數(shù): 1
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 42-VFQFN 裸露焊盤
供應商設備封裝: 42-QFN(8x8)
包裝: 管件
包括: PCM 通路
DS_1x66B_001
73M1866B/73M1966B Data Sheet
Rev. 1.6
15
Pin
Number
Pin Name
Type
Description
17
VND
GND
Negative digital ground
18
INT
O
Interrupt / ring detect (active low – open drain)
19
SCLK
I
SPI clock
20
CS
I
SPI chip select (active low)
21
DR
I
PCM transmit data sent to the D to A
22
SRE
I
Voltage regulator sense
23
SRB
O
Voltage regulator drive
24
VBG
O
VBG bypass, connect to 0.1μF capacitor to VNS
25
ACS
I
AC current sense
26
VNS
GND
Analog negative supply voltage
27
VPS
PWRO
Analog positive supply voltage (output)
28
RXP
I
Receive plus – signal input
29
RXM
I
Receive minus – signal input
30
TXM
O
Transmit Minus transhybrid cancellation output
31
DCD
O
DC loop output
32
DCS
I
DC loop current sense
33
DCG
O
DC loop control
34
DCI
I
DC loop input
35
RGN
I
Ring detect negative voltage input
36
RGP
I
Ring detect positive voltage input
37
OFH
O
Off-hook control
38
M20PB
I
Test pin. Connect to VNX.
39
VNX
GND
Negative supply voltage
40
SCP
I/O
Positive side of the secondary pulse transformer winding
41
MID
I/O
Charge pump midpoint
42
VPX
PWR
Supply from the barrier
2.6
Requisite Use of Exposed Bottom Pad on 73M1866B and 73M1966B QFN
Packages
The exposed bottom pad is not intended for thermal relief (heat dissipation) and should not be
soldered to the PCB. Soldering of the exposed pad could also compromise electrical
isolation/insulation requirements for proper voltage isolation. Avoid any PCB traces or through-hole
vias on the PCB beneath the exposed pad area.
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