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參數(shù)資料
| 型號： | 72V3684L15PF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | FIFO |
| 英文描述： | 16K X 36 BI-DIRECTIONAL FIFO, 10 ns, PQFP128 |
| 封裝： | TQFP-128 |
| 文件頁數(shù)： | 25/36頁 |
| 文件大?。?/td> | 418K |
| 代理商： | 72V3684L15PF |
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COMMERCIALTEMPERATURERANGE
IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFOTM WITH
BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65 and 536 x 36 x 2
31
Figure 26. Timing for
AFB when FIFO2 is Almost-Full (IDT Standard and FWFT Modes)
Figure 27. Timing for Mail1 Register and
MBF1 Flag (IDT Standard and FWFT Modes)
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for
AFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW2, then
AFB may transition HIGH one CLKB cycle later than shown.
2. FIFO2 write (
CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 16,384 for the IDT72V3684, 32,768 for the IDT72V3694, 65,536 for the IDT72V36104.
4. If Port B size is word or byte,
AFB is set LOW by the last word or byte write of the long word, respectively.
AFB
CLKB
ENA
4677 drw28
ENB
CLKA
12
tSKEW2
tENS2
tENH
tPAF
tENS2
tENH
tPAF
[D-(Y2+1)] Words in FIFO2
(D-Y2) Words in FIFO2
(1)
4677 drw29
CLKA
ENA
A0-A35
MBA
CSA
W/
RA
CLKB
MBF1
CSB
MBB
ENB
B0-B35
W/RB
W1
tENS1
tENH
tDS
tDH
tPMF
tENS2
tENH
tDIS
tEN
tMDV
tPMR
FIFO1 Output Register
W1 (Remains valid in Mail1 Register after read)
tENS1
tENH
tENS2
tENH
tENS2
tENH
NOTE:
1. If Port B is configured for word size, data can be written to the Mail1 register using A0-A17 (A18-A35 are don't care inputs). In this first case B0-B17 will have valid data (B18-B35
will be indeterminate). If Port B is configured for byte size, data can be written to the Mail1 Register using A0-A8 (A9-A35 are don't care inputs). In this second case, B0-B8 will
have valid data (B9-B35 will be indeterminate).
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| 72V3690L10PF | 功能描述:先進先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| 72V3690L10PF8 | 制造商:Integrated Device Technology Inc 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 32K x 36 128-Pin TQFP T/R 制造商:Integrated Device Technology Inc 功能描述:FIFO SYNC DUAL DEPTH/WIDTH UNI-DIR 32KX36 128TQFP - Tape and Reel |
| 72V3690L15PF | 功能描述:先進先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| 72V3690L15PF8 | 制造商:Integrated Device Technology Inc 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 32K x 36 128-Pin TQFP T/R 制造商:Integrated Device Technology Inc 功能描述:FIFO SYNC DUAL DEPTH/WIDTH UNI-DIR 32KX36 128TQFP - Tape and Reel |
| 72V3690L15PFI | 功能描述:先進先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
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