參數(shù)資料
型號(hào)： 72V3684L15PF
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： FIFO
英文描述： 16K X 36 BI-DIRECTIONAL FIFO, 10 ns, PQFP128
封裝： TQFP-128
文件頁(yè)數(shù)： 24/36頁(yè)
文件大?。?/td> 418K
代理商： 72V3684L15PF
COMMERCIALTEMPERATURERANGE
IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFOTM WITH
BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2 and 65, 536 x 36 x 2
30
Figure 25. Timing for
AFA when FIFO1 is Almost-Full (IDT Standard and FWFT Modes)
Figure 23. Timing for
AEB when FIFO1 is Almost-Empty (IDT Standard and FWFT Modes)
Figure 24. Timing for
AEA when FIFO2 is Almost-Empty (IDT Standard and FWFT Modes)
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for
AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW2, then
AEB may transition HIGH one CLKB cycle later than shown.
2. FIFO1 Write (
CSA = LOW, W/RA = LOW, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.
3. If Port B size is word or byte,
AEB is set LOW by the last word or byte read from FIFO1, respectively.
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for
AFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW2, then
AFA may transition HIGH one CLKA cycle later than shown.
2. FIFO1 Write (
CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 16,384 for the IDT72V3684, 32,768 for the IDT72V3694, 65,536 for the IDT72V36104.
4. If Port B size is word or byte, tSKEW2 is referenced to the rising CLKB edge that reads the last word or byte of the long word, respectively.
AEB
CLKA
ENB
4677 drw25
ENA
CLKB
2
1
tENS2
tENH
tSKEW2
tPAE
tENS2
tENH
X1 Words in FIFO1
(X1+1) Words in FIFO1
(1)
AEA
CLKB
ENA
4677 drw26
ENB
CLKA
2
1
tENS2
tENH
tSKEW2
tPAE
tENS2
tENH
(X2+1) Words in FIFO2
X2 Words in FIFO2
(1)
AFA
CLKA
ENB
4677 drw27
ENA
CLKB
12
tSKEW2
tENS2
tENH
tPAF
tENS2
tENH
tPAF
[D-(Y1+1)] Words in FIFO1
(D-Y1) Words in FIFO1
(1)
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for
AEA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW2, then
AEA may transition HIGH one CLKA cycle later than shown.
2. FIFO2 Write (
CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
3. If Port B size is word or byte, tSKEW2 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.
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72V3690L15PF 功能描述:先進(jìn)先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問(wèn)時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝:
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72V3690L15PFI 功能描述:先進(jìn)先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問(wèn)時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝:
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