參數(shù)資料
型號(hào)： 72V3684L15PF
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi)： FIFO
英文描述： 16K X 36 BI-DIRECTIONAL FIFO, 10 ns, PQFP128
封裝： TQFP-128
文件頁(yè)數(shù)： 35/36頁(yè)
文件大?。?/td> 418K
代理商： 72V3684L15PF
COMMERCIALTEMPERATURERANGE
IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFOTM WITH
BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2 and 65, 536 x 36 x 2
8
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
IDT72V3684L10
IDT72V3684L15
IDT72V3694L10
IDT72V3694L15
IDT72V36104L10
IDT72V36104L15
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
fS
Clock Frequency, CLKA or CLKB
—
100
—
66.7
MHz
tCLK
Clock Cycle Time, CLKA or CLKB
10
—
15
—
ns
tCLKH
Pulse Duration, CLKA or CLKB HIGH
4.5
—
6
—
ns
tCLKL
Pulse Duration, CLKA and CLKB LOW
4.5
—
6
—
ns
tDS
Setup Time, A0-A35 before CLKA
↑ and B0-B35 before CLKB↑
3—
4
—
ns
tENS1
Setup Time,
CSA and W/RA before CLKA
↑; CSB and
4
—
4.5
—
ns
W/RB before CLKB
↑
tENS2
Setup Time, ENA, and MBA before CLKA
↑; ENB, and
3
—
4.5
—
ns
MBB before CLKB
↑
tRSTS
Setup Time,
MRS1, MRS2, PRS1, or PRS2 LOW before
5
—
5
—
ns
CLKA
↑ orCLKB↑(1)
tFSS
Setup Time, FS0, FS1, FS2 before
MRS1 and MRS2 HIGH
7.5
—
7.5
—
ns
tBES
Setup Time, BE/
FWFT before MRS1 and MRS2 HIGH
7.5
—
7.5
—
ns
tSDS
Setup Time, FS0/SD before CLKA
↑
3—
4
—
ns
tSENS
Setup Time, FS1/
SEN before CLKA
↑
3—
4
—
ns
tFWS
Setup Time, BE/
FWFT before CLKA
↑
0—
0
—
ns
tRTMS
Setup Time, RTM before
RT1; RTM before RT2
5—
5
—
ns
tDH
Hold Time, A0-A35 after CLKA
↑ and B0-B35 after CLKB↑
0.5
—
1
—
ns
tENH
Hold Time,
CSA, W/RA, ENA, and MBA after CLKA
↑; CSB,
0.5
—
1
—
ns
W/RB, ENB, and MBB after CLKB
↑
tRSTH
Hold Time,
MRS1, MRS2, PRS1 or PRS2 LOW after CLKA
↑
4—
4
—
ns
or CLKB
↑(1)
tFSH
Hold Time, FS0, FS1, FS2 after
MRS1 and MRS2 HIGH
2
—
2
—
ns
tBEH
Hold Time, BE/
FWFT after MRS1 and MRS2 HIGH
2
—
2
—
ns
tSDH
Hold Time, FS0/SD after CLKA
↑
0.5
—
1
—
ns
tSENH
Hold Time, FS1/
SEN HIGH after CLKA
↑
0.5
—
1
—
ns
tSPH
Hold Time, FS1/
SEN HIGH after MRS1 and MRS2 HIGH
2
—
2
—
ns
tRTMH
Hold Time, RTM after
RT1; RTM after RT2
5—
5
—
ns
tSKEW1(2)
Skew Time between CLKA
↑and CLKB↑for EFA/ORA,
5
—
7.5
—
ns
EFB/ORB, FFA/IRA, and FFB/IRB
tSKEW2(2.3)
Skew Time between CLKA
↑ and CLKB↑ for AEA, AEB, AFA,12
—
12
—
ns
and
AFB
NOTES:
1. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
2. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
3. Design simulated, not tested.
(Vcc = 3.3V ± 0.15V; TA = 0ο C to +70ο C; JEDEC JESD8-A compliant)
相關(guān)PDF資料
PDF描述
72V845L15PFI8 4K X 18 BI-DIRECTIONAL FIFO, 10 ns, PQFP128
72V805L15PFI9 256 X 18 BI-DIRECTIONAL FIFO, 10 ns, PQFP128
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
72V3690L10PF 功能描述:先進(jìn)先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類(lèi)型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問(wèn)時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝:
72V3690L10PF8 制造商:Integrated Device Technology Inc 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 32K x 36 128-Pin TQFP T/R 制造商:Integrated Device Technology Inc 功能描述:FIFO SYNC DUAL DEPTH/WIDTH UNI-DIR 32KX36 128TQFP - Tape and Reel
72V3690L15PF 功能描述:先進(jìn)先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類(lèi)型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問(wèn)時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝:
72V3690L15PF8 制造商:Integrated Device Technology Inc 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 32K x 36 128-Pin TQFP T/R 制造商:Integrated Device Technology Inc 功能描述:FIFO SYNC DUAL DEPTH/WIDTH UNI-DIR 32KX36 128TQFP - Tape and Reel
72V3690L15PFI 功能描述:先進(jìn)先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類(lèi)型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問(wèn)時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝:
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