參數(shù)資料
型號: 72205LB25TFI
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: FIFO
英文描述: 256 X 18 OTHER FIFO, 15 ns, PQFP64
封裝: PLASTIC, STQFP-64
文件頁數(shù): 7/16頁
文件大?。?/td> 181K
代理商: 72205LB25TFI
15
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO
256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
Commercial And Industrial Temperature Ranges
DEPTH EXPANSION CONFIGURATION
(WITH PROGRAMMABLE FLAGS)
These devices can easily be adapted to applications requir-
ing more than 256/512/1,024/2,048/4,096 words of buffering.
Figure 21 shows Depth Expansion using three IDT72205LB/
72215LB/72225LB/72235LB/72245LBs. Maximum depth is
limited only by signal loading. Follow these steps:
1. The first device must be designated by grounding the
First Load (
FL) control input.
2. All other devices must have
FL in the HIGH state.
3. The Write Expansion Out (
WXO) pin of each device
must be tied to the Write Expansion In (
WXI) pin of
the next device. See Figure 21.
4. The Read Expansion Out (
RXO) pin of each device
must be tied to the Read Expansion In (
RXI) pin of
the next device. See Figure 21.
5. All Load (
LD) pins are tied together.
6. The Half-Full Flag (
HF) is not available in this Depth
Expansion Configuration.
7.
EF, FF, PAE, and PAF are created with composite
flags by ORing together every respective flags for
monitoring. The composite
PAE and PAF flags are not
precise.
Figure 21. Block Diagram of 768 x 18, 1,536 x 18, 3,072 x 18, 6,144 x 18, 12,288 x 18 Synchronous
FIFO Memory With Programmable Flags used in Depth Expansion Configuration
LOAD
WRITE CLOCK
WRITE ENABLE
READ CLOCK
READ ENABLE
OUTPUT ENABLE
DATA IN
DATA OUT
RESET
IDT
72205LB
72215LB
72225LB
72235LB
72245LB
FIRST LOAD (
)
Vcc
IDT
72205LB
72215LB
72225LB
72235LB
72245LB
IDT
72205LB
72215LB
72225LB
72235LB
72245LB
2766 drw 23
RCLK
WCLK
RCLK
WCLK
RCLK
WCLK
Dn
Qn
Dn
Qn
Dn
Qn
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PDF描述
72215LB10TFG8 512 X 18 OTHER FIFO, 6.5 ns, PQFP64
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