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參數(shù)資料
| 型號： | 72205LB25TFI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | FIFO |
| 英文描述： | 256 X 18 OTHER FIFO, 15 ns, PQFP64 |
| 封裝： | PLASTIC, STQFP-64 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 181K |
| 代理商： | 72205LB25TFI |
14
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
Commercial And Industrial Temperature Ranges
OPERATING CONFIGURATIONS
SINGLE DEVICE CONFIGURATION
A single IDT72205LB/72215LB/72225LB/72235LB/72245LB
may be used when the application requirements are for 256/
512/1,024/2,048/4,096 words or less. These FIFOs are in a
single Device Configuration when the First Load (
FL), Write
Expansion In (
WXI) and Read Expansion In (RXI) control inputs
are grounded (Figure 19).
Figure 19. Block Diagram of Single 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18 Synchronous FIFO
NOTE:
1. Do not connect any output control signals directly together.
Figure 20. Block Diagram of 256 x 36, 512 x 36, 1,024 x 36, 2,048 x 36, 4,096 x 36
Synchronous FIFO Memory Used in a Width Expansion Configuration
WRITE CLOCK (WCLK)
WRITE ENABLE (
)
READ CLOCK (RCLK)
READ ENABLE (
)
LOAD (
)
OUTPUT ENABLE (
)
DATA IN (D0 - D17)
DATA OUT (Q0 - Q17)
FULL FLAG (
)
PROGRAMMABLE (
)
HALF-FULL FLAG (
)
EMPTY FLAG (
)
PROGRAMMABLE (
)
RESET (
)
IDT
72205LB
72215LB
72225LB
72235LB
72245LB
2766 drw 21
FIRST LOAD (
)
READ EXPANSION IN (
)
WRITE EXPANSION IN (
)
WRITE CLOCK (WCLK)
WRITE ENABLE (
)
READ CLOCK (RCLK)
READ ENABLE (
)
LOAD (
)
OUTPUT ENABLE (
)
DATA IN (D)
DATA OUT (Q)
FULL FLAG (
)
PROGRAMMABLE (
)
HALF FULL FLAG (
)
EMPTY FLAG (
)
PROGRAMMABLE (
)
RESET (
)
72205LB
72215LB
72225LB
72235LB
72245LB
72205LB
72215LB
72225LB
72235LB
72245LB
RESET (
)
36
18
2766 drw 22
FIRST LOAD (
)
READ EXPANSION IN (
)
WRITE EXPANSION IN (
)
WIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting together
the control signals of multiple devices. Status flags can be
detected from any one device. The exceptions are the Empty
Flag and Full Flag. Because of variations in skew between
RCLK and WCLK, it is possible for flag assertion and deassertion
to vary by one cycle between FIFOs. To avoid problems the
user must create composite flags by ANDing the Empty Flags
of every FIFO, and separately ANDing all Full Flags. Figure 20
demonstrates a 36-word width by using two IDT72205B/72215B/
72225B/72235B/72245Bs. Any word width can be attained by
adding additional IDT72205B/72215B/72225B/72235B/
72245Bs. Please see the Application Note AN-83.
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PDF描述 |
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| 72215LB10TFG8 | 512 X 18 OTHER FIFO, 6.5 ns, PQFP64 |
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| IDT72235LB25TF | CMOS SyncFIFOO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18 |
| IDT72235LB25TFI | CMOS SyncFIFOO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18 |
| IDT72235LB25TFB | CMOS SyncFIFOO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18 |
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參數(shù)描述 |
|---|---|
| 72205LB25TFI8 | 制造商:Integrated Device Technology Inc 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 256 x 18 64-Pin STQFP T/R 制造商:Integrated Device Technology Inc 功能描述:FIFO SYNC DUAL DEPTH/WIDTH UNI-DIR 256 X 18 64TQFP - Tape and Reel |
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