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參數(shù)資料
| 型號(hào)： | 72205LB15PFI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | FIFO |
| 英文描述： | 256 X 18 OTHER FIFO, 10 ns, PQFP64 |
| 封裝： | PLASTIC, TQFP-64 |
| 文件頁(yè)數(shù)： | 2/16頁(yè) |
| 文件大小： | 181K |
| 代理商： | 72205LB15PFI |
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IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
Commercial And Industrial Temperature Ranges
Figure 7. First Data Word Latency after Reset with Simultaneous Read and Write
Figure 8. Full Flag Timing
WCLK
D0 - D17
RCLK
Q0 - Q17
t DS
tSKEW2
t ENS
t REF
tA
0
12
3
D
DDD
01
DD
(first valid write)
t OE
t OLZ
tA
tFRL(1)
D4
tENS
2766 drw 09
NOTE:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that
FF will go HIGH during the current clock cycle. If the
time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then
FF may not change state until the next WCLK edge.
DATA READ
WCLK
D0 - D17
RCLK
Q0 - Q17
t A
t WFF
DATA WRITE
t WFF
t ENH
t ENS
t DS
t WFF
t DS
DATA
WRITE
NEXT DATA READ
t A
NO WRITE
DATA IN OUTPUT REGISTER
LOW
tSKEW1
(1)
t SKEW1
(1)
t ENH
t ENS
2766 drw 10
NOTES:
1. When tSKEW2 minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either
2*tCLK + tSKEW2 or tCLK + tSKEW2. The Latency Timing applies only at the Empty Boundary (
EF = LOW).
2. The first word is available the cycle after
EF goes HIGH, always.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 72205LB25TFI | 256 X 18 OTHER FIFO, 15 ns, PQFP64 |
| 72215LB10TFG8 | 512 X 18 OTHER FIFO, 6.5 ns, PQFP64 |
| 72215LB15J8 | 512 X 18 OTHER FIFO, 10 ns, PQCC68 |
| IDT72235LB25TF | CMOS SyncFIFOO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18 |
| IDT72235LB25TFI | CMOS SyncFIFOO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 72205LB15PFI8 | 制造商:Integrated Device Technology Inc 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 256 x 18 64-Pin TQFP T/R 制造商:Integrated Device Technology Inc 功能描述:FIFO SYNC DUAL DEPTH/WIDTH UNI-DIR 256 X 18 64TQFP - Tape and Reel |
| 72205LB15TF | 功能描述:先進(jìn)先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類(lèi)型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問(wèn)時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| 72205LB15TF8 | 制造商:Integrated Device Technology Inc 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 256 x 18 64-Pin STQFP T/R 制造商:Integrated Device Technology Inc 功能描述:FIFO SYNC DUAL DEPTH/WIDTH UNI-DIR 256 X 18 64TQFP - Tape and Reel |
| 72205LB15TFI | 制造商:Integrated Device Technology Inc 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 256 x 18 64-Pin STQFP 制造商:Integrated Device Technology Inc 功能描述:FIFO SYNC DUAL DEPTH/WIDTH UNI-DIR 256 X 18 64TQFP - Rail/Tube |
| 72205LB15TFI8 | 制造商:Integrated Device Technology Inc 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 256 x 18 64-Pin STQFP T/R 制造商:Integrated Device Technology Inc 功能描述:FIFO SYNC DUAL DEPTH/WIDTH UNI-DIR 256 X 18 64TQFP - Tape and Reel |
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