參數(shù)資料
型號： 72205LB15PFI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： FIFO
英文描述： 256 X 18 OTHER FIFO, 10 ns, PQFP64
封裝： PLASTIC, TQFP-64
文件頁數(shù)： 12/16頁
文件大?。?/td> 181K
代理商： 72205LB15PFI
5
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO
256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
Commercial And Industrial Temperature Ranges
NOTES:
1. Industrial temperature range is available as standard product for the 15ns
and the 25ns speed grade.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.
2766 tbl 07
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V
± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C)
Commercial
Com'l & Ind'l
(1)
72205LB10
72205LB15
72205LB25
72215LB10
72215LB15
72215LB25
72225LB10
72225LB15
72225LB25
72235LB10
72235LB15
72235LB25
72245LB10
72245LB15
72245LB25
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
fS
Clock Cycle Frequency
—
100
—
66.7
—
40
MHz
tA
Data Access Time
2
6.5
2
10
2
15
ns
tCLK
Clock Cycle Time
10
—
15
—
25
—
ns
tCLKH
Clock HIGH Time
4.5
—
6
—
10
—
ns
tCLKL
Clock LOW Time
4.5
—
6
—
10
—
ns
tDS
Data Set-up Time
3—4—
6—
ns
tDH
Data Hold Time
0—1—
1—
ns
tENS
Enable Set-up Time
3—4—
6—
ns
tENH
Enable Hold Time
0—1—
1—
ns
tRS
Reset Pulse Width(2)
10
—
15
—
25
—
ns
tRSS
Reset Set-up Time
8
—
10
—
15
—
ns
tRSR
Reset Recovery Time
8
—
10
—
15
—
ns
tRSF
Reset to Flag and Output Time
—
15
—
20
—
25
ns
tOLZ
Output Enable to Output in Low-Z(3)
0—0—
0—
ns
tOE
Output Enable to Output Valid
3638
3
12
ns
tOHZ
Output Enable to Output in High-Z(3)
3638
3
12
ns
tWFF
Write Clock to Full Flag
—
6.5
—
10
—
15
ns
tREF
Read Clock to Empty Flag
—
6.5
—
10
—
15
ns
tPAF
Clock to Programmable Almost-Full
—
17
—
24
—
26
ns
Flag
tPAE
Clock to Programmable Almost-Empty
—
17
—
24
—
26
ns
Flag
tHF
Clock to Half-Full Flag
—
17
—
24
—
26
ns
tXO
Clock to Expansion Out
—
6.5
—
10
—
15
ns
tXI
Expansion In Pulse Width
3
—
6.5
—
10
—
ns
tXIS
Expansion In Set-Up Time
3.5
—
5
—
10
—
ns
tSKEW1
Skew time between Read Clock &
5—6—
10
—
ns
Write Clock for Full Flag
tSKEW2
Skew time between Read Clock &
5—6—
10
—
ns
Write Clock for Empty Flag
Figure 1. Output Load
* Includes jig and scope capacitances.
30pF*
1.1K
5V
680
D.U.T.
2766 drw 04
相關(guān)PDF資料
PDF描述
72205LB25TFI 256 X 18 OTHER FIFO, 15 ns, PQFP64
72215LB10TFG8 512 X 18 OTHER FIFO, 6.5 ns, PQFP64
72215LB15J8 512 X 18 OTHER FIFO, 10 ns, PQCC68
IDT72235LB25TF CMOS SyncFIFOO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18
IDT72235LB25TFI CMOS SyncFIFOO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
72205LB15PFI8 制造商:Integrated Device Technology Inc 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 256 x 18 64-Pin TQFP T/R 制造商:Integrated Device Technology Inc 功能描述:FIFO SYNC DUAL DEPTH/WIDTH UNI-DIR 256 X 18 64TQFP - Tape and Reel
72205LB15TF 功能描述:先進(jìn)先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝:
72205LB15TF8 制造商:Integrated Device Technology Inc 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 256 x 18 64-Pin STQFP T/R 制造商:Integrated Device Technology Inc 功能描述:FIFO SYNC DUAL DEPTH/WIDTH UNI-DIR 256 X 18 64TQFP - Tape and Reel
72205LB15TFI 制造商:Integrated Device Technology Inc 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 256 x 18 64-Pin STQFP 制造商:Integrated Device Technology Inc 功能描述:FIFO SYNC DUAL DEPTH/WIDTH UNI-DIR 256 X 18 64TQFP - Rail/Tube
72205LB15TFI8 制造商:Integrated Device Technology Inc 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 256 x 18 64-Pin STQFP T/R 制造商:Integrated Device Technology Inc 功能描述:FIFO SYNC DUAL DEPTH/WIDTH UNI-DIR 256 X 18 64TQFP - Tape and Reel
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