參數(shù)資料
型號(hào): 71V016SA12PHGI8
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi): SRAM
英文描述: 64K X 16 STANDARD SRAM, 12 ns, PDSO44
封裝: 0.400 INCH, ROHS COMPLIANT, TSOP2-44
文件頁(yè)數(shù): 7/9頁(yè)
文件大?。?/td> 283K
代理商: 71V016SA12PHGI8
6.42
7
IDT71V016SA, 3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,4)
NOTES:
1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.
2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ+ tDW to allow the I/O drivers to turn off and data to be placed
on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP.
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. IftheCS LOWor BHEandBLE LOWtransitionoccurssimultaneouslywithorafterthe WELOWtransition,theoutputsremaininahigh-impedancestate.
5. Transitionismeasured±200mVfromsteadystate.
Timing Waveform of Write Cycle No. 3 (BHE, BLE Controlled Timing)(1,4)
ADDRESS
CS
DATAIN
3834 drw 09
DATAIN VALID
tWC
tAS
(2)
tCW
tWR
WE
tAW
DATAOUT
tDW
tDH
BHE, BLE
tBW
tWP
ADDRESS
CS
DATAIN
3834 drw 10
DATAIN VALID
tWC
tAS
(2)
tCW
tWR
WE
tAW
DATAOUT
tDW
tDH
BHE, BLE
tBW
tWP
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