參數(shù)資料
型號: 71V016SA12PHGI8
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: SRAM
英文描述: 64K X 16 STANDARD SRAM, 12 ns, PDSO44
封裝: 0.400 INCH, ROHS COMPLIANT, TSOP2-44
文件頁數(shù): 1/9頁
文件大小: 283K
代理商: 71V016SA12PHGI8
OCTOBER 2011
DSC-3834/11
1
2011 Integrated Device Technology, Inc.
Features
64K x 16 advanced high-speed CMOS Static RAM
Equal access and cycle times
— Commercial:10/12/15/20ns
— Industrial:12/15/20ns
One Chip Select plus one Output Enable pin
Bidirectional data inputs and outputs directly
LVTTL-compatible
Low power consumption via chip deselect
Upper and Lower Byte Enable Pins
Single 3.3V power supply
Available in 44-pin Plastic SOJ, 44-pin TSOP, and
48-Ball Plastic FBGA packages
Description
TheIDT71V016isa1,048,576-bithigh-speedStaticRAMorganized
as64Kx16.ItisfabricatedusingIDT’shigh-perfomance,high-reliability
CMOStechnology.Thisstate-of-the-arttechnology,combinedwithinno-
vativecircuitdesigntechniques,providesacost-effectivesolutionforhigh-
speedmemoryneeds.
The IDT71V016 has an output enable pin which operates as fast
as 5ns, with address access times as fast as 10ns. All bidirectional
inputsandoutputsoftheIDT71V016areLVTTL-compatibleandoperation
is from a single 3.3V supply. Fully static asynchronous circuitry is used,
requiring no clocks or refresh for operation.
The IDT71V016 is packaged in a JEDEC standard 44-pin Plastic
SOJ, a 44-pin TSOP Type II, and a 48-ball plastic 7 x 7 mm FBGA.
Functional Block Diagram
Output
Enable
Buffer
Address
Buffers
Chip
Enable
Buffer
Write
Enable
Buffer
Byte
Enable
Buffers
OE
A0 –A15
Row / Column
Decoders
CS
WE
BHE
BLE
64K x 16
Memory
Array
Sense
Amps
and
Write
Drivers
16
Low
Byte
I/O
Buffer
8
I/O8
I/O15
I/O7
I/O0
3834 drw 01
High
Byte
I/O
Buffer
3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
IDT71V016SA
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相關(guān)代理商/技術(shù)參數(shù)
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