71M6533/71M6534 Data Sheet
FDS_6533_6534_004
6
2007-2009 TERIDIAN Semiconductor Corporation
v1.1
Tables
Table 11: PSW Bit Functions (SFR 0xD0) ................................................................................................... 23
Table 17: The S0CON (UART0) Register (SFR 0x98)................................................................................. 28
Table 18: The S1CON (UART1) Register (SFR 0x9B) ................................................................................ 28
Table 22: TMOD Register Bit Description (SFR 0x89)................................................................................ 29
Table 23: The TCON Register Bit Functions (SFR 0x88)............................................................................ 30
Table 24: The IEN0 Bit Functions (SFR 0xA8)............................................................................................ 31
Table 25: The IEN1 Bit Functions (SFR 0xB8)............................................................................................ 31
Table 26: The IEN2 Bit Functions (SFR 0x9A)............................................................................................ 31
Table 27: TCON Bit Functions (SFR 0x88) ................................................................................................. 32
Table 28: The T2CON Bit Functions (SFR 0xC8)....................................................................................... 32
Table 29: The IRCON Bit Functions (SFR 0xC0) ........................................................................................ 32
Table 41: EECTRL Bits for 2-pin Interface................................................................................................... 47
Table 42: EECTRL Bits for the 3-wire Interface ........................................................................................... 47
Table 44: TMUX[4:0] Selections ................................................................................................................. 52
Table 48: CE EQU Equations and Element Input Mapping ........................................................................ 92
Table 50: CESTATUS Register..................................................................................................................... 93
Table 51: CESTATUS Bit Definitions ............................................................................................................ 93
Table 52: CECONFIG Register.................................................................................................................... 93
Table 53: CECONFIG Bit Definitions ........................................................................................................... 94