參數(shù)資料
型號: 71M6534-IGTR/F
廠商: TERIDIAN SEMICONDUCTOR CORP
元件分類: 模擬信號調(diào)理
英文描述: SPECIALTY ANALOG CIRCUIT, PQFP120
封裝: LEAD FREE, LQFP-120
文件頁數(shù): 78/124頁
文件大?。?/td> 2008K
代理商: 71M6534-IGTR/F
FDS_6533_6534_004
71M6533/71M6534 Data Sheet
v1.1
2007-2009 TERIDIAN Semiconductor Corporation
57
2.3.2
LCD Mode
In LCD mode, the data contained in the LCD_SEG registers is displayed. Up to four LCD segments con-
nected to the pin SEG18 can be made to blink without the involvement of the MPU, which is disabled in
LCD mode. To minimize power, only segments that might be used should be enabled.
LCD mode can be exited only by system power up, a timeout of the wake-up timer, or a push button.
When the IC exits LCD mode, the MPU can discover the event that caused the exit by reading the inter-
rupt flags and interpret them as follows:
IE_WAKE = 1 indicates that the wake timer has expired.
IE_PB =1 indicates that the pushbutton input (PB) was activated.
COMPSTAT = 0 indicates that a reset occurred but that main power is not yet available.
If none of the above conditions applies, system power (V3P3SYS) must have been restored
After the transition from LCD mode to MISSION or BROWNOUT mode, the PC will be at 0x0000, the
XRAM is in an undefined state, and the I/O RAM is only partially preserved (see the description of I/O
RAM states in 4.2). GP0[7:0] through GP7[7:0] are preserved unless a hardware reset occurs (RESET
pin is pulled high or power to the part is cycled without a battery being present). Figure 22 shows the
functional blocks active in LCD mode.
2.3.3
SLEEP Mode
In SLEEP mode, the battery current is minimized and only the Oscillator and RTC functions are active.
This mode can be exited only by system power-up, a timeout of the wake-up timer, or a push button
event.
When the IC exits SLEEP mode, the MPU can discover the event that caused the exit by reading the in-
terrupt flags and interpret them as follows:
IE_WAKE = 1 indicates that the wake timer has expired.
IE_PB =1 indicates that the pushbutton input (PB) was activated.
COMPSTAT = 0 indicates that a reset occurred but that main power is not yet available.
If none of the above conditions applies, system power (V3P3SYS) must have been restored
After the transition from SLEEP mode to MISSION or BROWNOUT mode the PC will be at 0x0000, the
XRAM is in an undefined state, and the I/O RAM is only partially preserved (see the description of I/O
RAM states in 4.2). GP0[7:0] through GP7[7:0] are preserved unless the a hardware reset occurs
(RESET pin is pulled high or power to the part is cycled without a battery being present). Figure 23
shows the functional blocks active in SLEEP mode.
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