參數(shù)資料
型號(hào): 71M6532D-IGTR/F
廠商: TERIDIAN SEMICONDUCTOR CORP
元件分類: 電源管理
英文描述: 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQFP100
封裝: LEAD FREE, LQFP-100
文件頁數(shù): 103/120頁
文件大?。?/td> 2477K
代理商: 71M6532D-IGTR/F
FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
v1.3
2005-2010 TERIDIAN Semiconductor Corporation
83
Name
Location
Reset
Wake
Dir
Description
LCD_SEG33[3:0]
LCD_SEG35[3:0]
2051[3:0]
2053[3:0]
0
0
L
L
R/W
R/W
LCD_SEG37[3:0]
2055[3:0]
0
L
R/W
LCD_SEG39[3:0]
LCD_SEG41[3:0]
2057[3:0]
2059[3:0]
0
0
L
L
R/W
R/W
LCD_SEG48[7:4]
LCD_SEG49[7:4]
2036[7:4]
2037[7:4]
0
0
L
L
R/W
R/W
LCD_SEG63[7:4]
LCD_SEG66[7:4]
2045[7:4]
2048[7:4]
0
0
L
L
R/W
R/W
LCD_SEG71[7:4]
LCD_SEG73[7:4]
204D[7:4]
204F[7:4]
0
0
L
L
R/W
R/W
LCD_Y
2021[6]
0
L
R/W
LCD Blink Frequency (ignored if blink is disabled or if the segment is off).
0 = 1 Hz (500 ms ON, 500 ms OFF)
1 = 0.5 Hz (1 s ON, 1 s OFF)
M26MHZ
M40MHZ
2005[4]
2005[0]
0
R/W
M26MHZ and M40MHZ set the master clock (MCK) frequency. These bits are reset on
chip reset and may only be set. Attempts to write zeroes to M40MHZ and M26MHZ.are
ignored.
MPU_DIV[2:0]
2004[2:0]
0
R/W
The MPU clock divider (from MCK). These bits may be programmed by MPU without
risk of losing control.
MPU_DIV[2:0]
Resulting Clock Frequency
000
MCK/2
2
001
MCK/2
3
010
MCK/2
4
011
MCK/2
5
100
MCK/2
6
101
MCK/2
7
110
MCK/2
8
111
MCK/2
8
相關(guān)PDF資料
PDF描述
71M6532F-IGT/F 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQFP100
71M6531D-IM/F 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC68
71M6531F-IMR/F 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC68
71M6531F-IM/F 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC68
71M6532D-IGTR/F 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQFP100
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