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| 型號： | 70V9389L9PRFI8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 64K X 18 DUAL-PORT SRAM, 20 ns, PQFP128 |
| 封裝： | TQFP-128 |
| 文件頁數(shù)： | 9/19頁 |
| 文件大?。?/td> | 211K |
| 代理商： | 70V9389L9PRFI8 |
6.42
IDT70V9389/289L
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
Industrial & Commercial Temperature Ranges
17
Depth and Width Expansion
TheIDT70V9389/289featuresdualchipenables(refertoTruthTable
I) in order to facilitate rapid and simple depth expansion with no require-
mentsforexternallogic.Figure4illustrateshowtocontrolthevarioiuschip
enables in order to expand two devices in depth.
The IDT70V9389/289 can also be used in applications requiring
expanded width, as indicated in Figure 4. Since the banks are allocated
at the discretion of the user, the external controller can be set up to drive
the input signals for the various devices as required to allow for 36/32-bit
or wider applications.
4856 drw 18
IDT70V9389/289
CE0
CE1
Control Inputs
CE1
CE0
IDT70V9389/289
Control Inputs
CE0
CE1
IDT70V9389/289
Control Inputs
A16
CE1
CE0
VDD
IDT70V9389/289
Control Inputs
CNTRST
CLK
ADS
CNTEN
R/
W
LB, UB
OE
Figure 4. Depth and Width Expansion with IDT70V9389/289
Functional Description
The IDT70V9389/289 provides a true synchronous Dual-Port Static
RAM interface. Registered inputs provide minimal set-up and hold times
on address, data, and all critical control inputs. All internal registers are
clocked on the rising edge of the clock signal, however, the self-timed
internalwritepulseisindependentoftheLOWtoHIGHtransitionoftheclock
signal.
An asynchronous output enable is provided to ease asynchronous
bus interfacing. Counter enable inputs are also provided to staff the
operationoftheaddresscountersforfastinterleavedmemoryapplications.
CE0=VIHorCE1=VILforoneclockcyclewillpowerdowntheinternal
circuitry to reduce static power consumption. Multiple chip enables allow
easier banking of multiple IDT70V9389/289's for depth expansion con-
figurations. When the Pipelined output mode is enabled, two cycles are
required with
CE0 = VIL and CE1 = VIH to re-activate the outputs.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT70V9289L9PRF8 | 64K X 16 DUAL-PORT SRAM, 20 ns, PQFP128 |
| 710026-3 | 25 mm2, COPPER ALLOY, TIN FINISH, WIRE TERMINAL |
| 710027-5 | 35 mm2, COPPER ALLOY, TIN FINISH, WIRE TERMINAL |
| 710027-2 | 35 mm2, COPPER ALLOY, TIN FINISH, WIRE TERMINAL |
| 710027-1 | 35 mm2, COPPER ALLOY, TIN FINISH, WIRE TERMINAL |
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