參數(shù)資料
型號(hào)： 70V9389L9PRFI8
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： SRAM
英文描述： 64K X 18 DUAL-PORT SRAM, 20 ns, PQFP128
封裝： TQFP-128
文件頁數(shù)： 2/19頁
文件大小： 211K
代理商： 70V9389L9PRFI8
6.42
10
IDT70V9389/289L
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
Industrial & Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)(3) (VDD = 3.3V ± 0.3V, TA = 0°C to +70°C)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device characteriza-
tion, but is not production tested.
2. The Pipelined output parameters (tCYC2, tCD2) apply to either or both the Left and Right ports when
FT/PIPE = VIH. Flow-through parameters (tCYC1, tCD1) apply
when
FT/PIPE = VIL for that port.
3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (
OE), FT/PIPER, and FT/PIPEL.
70V9389/289L6
Com'l Only
70V9389/289L7
Com'l Only
70V9389/289L9
Com'l & Ind
70V9389/289L12
Com'l Only
Symbol
Parameter
Min.Max.Min.Max.Min.
Max.Min.Max.
Unit
tCYC1
Clock Cycle Time (Flow-Through)(2)
19
____
22
____
25
____
30
____
ns
tCYC2
Clock Cycle Time (Pipelined)(2)
10
____
12
____
15
____
20
____
ns
tCH1
Clock High Time (Flow-Through)(2)
6.5
____
7.5
____
12
____
12
____
ns
tCL1
Clock Low Time (Flow-Through)(2)
6.5
____
7.5
____
12
____
12
____
ns
tCH2
Clock High Time (Pipelined)(2)
4
____
5
____
6
____
8
____
ns
tCL2
Clock Low Time (Pipelined)(2)
4
____
5
____
6
____
8
____
ns
tR
Clock Rise Time
____
3
____
3
____
3
____
3ns
tF
Clock Fall Time
____
3
____
3
____
3
____
3ns
tSA
Address Setup Time
3.5
____
4
____
4
____
4
____
ns
tHA
Address Hold Time
0
____
0
____
1
____
1
____
ns
tSC
Chip Enable Setup Time
3.5
____
4
____
4
____
4
____
ns
tHC
Chip Enable Hold Time
0
____
0
____
1
____
1
____
ns
tSB
Byte Enable Setup Time
3.5
____
4
____
4
____
4
____
ns
tHB
Byte Enable Hold Time
0
____
0
____
1
____
1
____
ns
tSW
R/W Setup Time
3.5
____
4
____
4
____
4
____
ns
tHW
R/W Hold Time
0
____
0
____
1
____
1
____
ns
tSD
Input Data Setup Time
3.5
____
4
____
4
____
4
____
ns
tHD
Input Data Hold Time
0
____
0
____
1
____
1
____
ns
tSAD
ADS Setup Time
3.5
____
4
____
4
____
4
____
ns
tHAD
ADS Hold Time
0
____
0
____
1
____
1
____
ns
tSCN
CNTEN Setup Time
3.5
____
4
____
4
____
4
____
ns
tHCN
CNTEN Hold Time
0
____
0
____
1
____
1
____
ns
tSRST
CNTRST Setup Time
3.5
____
4
____
4
____
4
____
ns
tHRST
CNTRST Hold Time
0
____
0
____
1
____
1
____
ns
tOE
Output Enable to Data Valid
____
6.5
____
7.5
____
9
____
12
ns
tOLZ
Output Enable to Output Low-Z(1)
2
____
2
____
2
____
2
____
ns
tOHZ
Output Enable to Output High-Z(1)
17
1
7
ns
tCD1
Clock to Data Valid (Flow-Through)(2)
____
15
____
18
____
20
____
25
ns
tCD2
Clock to Data Valid (Pipelined)(2)
____
6.5
____
7.5
____
9
____
12
ns
tDC
Data Output Hold After Clock High
2
____
2
____
2
____
2
____
ns
tCKHZ
Clock High to Output High-Z(1)
29
2
9
ns
tCKLZ
Clock High to Output Low-Z(1)
2
____
2
____
2
____
2
____
ns
Port-to-Port Delay
tCWDD
Write Port Clock High to Read Data Delay
____
24
____
28
____
35
____
40
ns
tCCS
Clock-to-Clock Setup Time
____
9
____
10
____
15
____
15
ns
4856 tbl 11
相關(guān)PDF資料
PDF描述
IDT70V9289L9PRF8 64K X 16 DUAL-PORT SRAM, 20 ns, PQFP128
710026-3 25 mm2, COPPER ALLOY, TIN FINISH, WIRE TERMINAL
710027-5 35 mm2, COPPER ALLOY, TIN FINISH, WIRE TERMINAL
710027-2 35 mm2, COPPER ALLOY, TIN FINISH, WIRE TERMINAL
710027-1 35 mm2, COPPER ALLOY, TIN FINISH, WIRE TERMINAL
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