參數(shù)資料
型號: 70P249L65BYGI
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: SRAM
英文描述: 4K X 16 DUAL-PORT SRAM, 40 ns, PBGA100
封裝: 0.50 MM PITCH, GREEN, BGA-100
文件頁數(shù): 14/22頁
文件大?。?/td> 146K
代理商: 70P249L65BYGI
6.42
21
IDT70P269/259/249L
Low Power 16K/8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
OCTOBER 16, 2008
Input Read Register
The Input Read Register (IRR) of the IDT70P269/259/249 captures
thestatusoftwoexternalbinaryinputdevicesconnectedtotheInputRead
pins (e.g. DIP switches). The contents of the IRR are read as a standard
memory access to address x0000 from either port and the data is output
via the standard I/Os (Truth Table V). During Input Register reads I/O0
- I/O1 are valid bits and I/O2 - I/O15 are read from the memory. Writes to
addressx0000arenormalmemoryoperation.When
SFEN=VIH,theIRR
is inactive and address x0000 can be used as part of the main memory.
The IRR inputs will be 1.8V/2.5V LVCMOS or 3.0V LVTTL, depending
on the core voltage supply.Refer to Truth Table V for Input Read Register
operation.
Output Drive Register
The Output Drive Register (ODR) of the IDT70P269/259/249 deter-
mines the state of up to five external binary-state devices by providing a
path to VSSfor the external circuit. The five external devices supported by
theODRcanoperateatdifferentvoltages(1.5V <VSUPPLY <3.5V),butthe
combinedcurrentofthedevicesmustnotexceed40mA(8mAIMAXforeach
external device). The status of the ODR bits is set using standard write
accessesfromeitherporttoaddressx0001witha“1”correspondingto“on“
and a “0” corresponding to “off”. The status of the ODR bits can also be
read(withoutchangingthestatusofthebits)viaastandardreadtoaddress
x0001. When
SFEN = VIL, the ODR is active and address x0001 is not
available for standard memory operations. When
SFEN = VIH, the ODR
is inactive and address x0001 can be used as part of the main memory.
During reads and writes to the ODR I/O0 - I/O4 are valid bits and I/O5 -
I/O15 will not affect the ODR function but they will read from or write to the
memory. Refer to Truth Table VI for Output Drive Register operation.
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