參數(shù)資料
型號: 70P249L65BYGI
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: SRAM
英文描述: 4K X 16 DUAL-PORT SRAM, 40 ns, PBGA100
封裝: 0.50 MM PITCH, GREEN, BGA-100
文件頁數(shù): 11/22頁
文件大?。?/td> 146K
代理商: 70P249L65BYGI
6.42
19
IDT70P269/259/249L
Low Power 16K/8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
OCTOBER 16, 2008
Truth Table V — Input Read Register Operation(3)
NOTES:
1.
UB or LB = VIL. If LB = VIL, then I/O0 - I/O7 are VALID. If UB = VIL, then I/O8 - I/O15 are VALID.
2.
LB must be active (LB = VIL) for these bits to be valid.
3.
SFEN = VIL to activate IRR reads.
4.
Valid data bits from memory.
SFEN
CE
R/
W
OE
UB
LB
ADDR
I/O0-I/O4
I/O5-I/O15
Mode
HL
H
X(1)
L(2)
x0000 - Max
VALID(2)
Standard Memory Access
LLL
X
L
x0001
VALID
(3)
VALID
(4)
ODR Write
(4,5)
L
H
L
X
L
x0001
VALID(3)
VALID(6)
ODR Read(5)
7146 tbl 19
Truth Table VI — Output Drive Register Operation(5)
NOTES:
1. Output enable must be low (OE = Vil) during reads for valid data to be output.
2.
UB or LB = VIL. If LB = VIL, then I/O0 - I/O7 are VALID. If UB = VIL, then I/O8 - I/O15 are VALID.
3.
LB must be active (LB = VIL) for these bits to be valid.
4. During ODR writes data will also be written to the memory.
5.
SFEN = VIL to activate ODR reads and writes.
6.
Valid data bits from memory.
SFEN
CS
WE
OE
UB
LB
ADDR
I/O0-I/O1
I/O2-I/O15
Mode
HL
H
L
L(1)
x0000 - Max
VALID(1)
Standard Memory Access
L
H
L
X
L
x0000
VALID(2)
VALID(4)
IRR Read(3)
7146 tbl 18
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