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參數(shù)資料
| 型號(hào)： | 70P249L65BYGI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 4K X 16 DUAL-PORT SRAM, 40 ns, PBGA100 |
| 封裝： | 0.50 MM PITCH, GREEN, BGA-100 |
| 文件頁數(shù)： | 13/22頁 |
| 文件大?。?/td> | 146K |
| 代理商： | 70P249L65BYGI |
6.42
IDT70P269/259/249L
Low Power 16K/8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
20
OCTOBER 16, 2008
Standard SRAM Interface Read/
Write Operation
The description of this section is applicable to either port when
configuredtooperateinStandardSRAMmode. Read/writeoperationwith
standardSRAMinterfaceconfigurationisthesameastheADMportexcept
addresses are presented on the address bus. Operation is controlled by
CS, OEand WE. AreadoperationisissuedwhenWEisassertedHIGH.
A write operation is issued when
WEisassertedLOW. TheI/Obusisthe
destination for read data and the source data for write data when the read
operationisissued. However,writedataneedstobedriventotheI/Owhen
the write operation is issued.
Interrupts
Iftheuserchoosestheinterruptfunction,amemorylocation(mailbox
or message center) is assigned to each port. The left port interrupt flag
(
INTL) is asserted when the right port writes to memory location 3FFE
(HEX) (1FFE for IDT70P259 and FFE for IDT70P249), where a write
is defined as the
CS=WE=VIL per Truth Table III. The left port clears the
interruptbyaccessingaddresslocation3FFEwhen
CSR=OER=VIL,WE
is a "don't care". Likewise, the right port interrupt flag (
INTR) is asserted
when the left port writes to memory location 3FFF (HEX) (1FFF for
IDT70P259 and FFF for IDT70P249) and to clear the interrupt flag
(
INTR),therightportmustreadthememorylocation3FFF.Themessage
(16bits)at3FFEor3FFFisuser-defined,sinceitisanaddressableSRAM
location. If the interrupt function is not used, address locations 3FFE and
3FFF are not used as mail boxes, but as part of the random access
memory. Refer to Truth Table III for the interrupt operation.
Busy Logic
BusyLogicprovidesahardwareindicationthatbothportsoftheSRAM
haveaccessedthesamelocationatthesametime.Italsoallowsoneofthe
twoaccessestoproceedandsignalstheothersidethattheSRAMis“busy”.
The
BUSY pincanthenbeusedtostalltheaccessuntiltheoperationon
the other side is completed. If a write operation has been attempted from
thesidethatreceivesa
BUSYindication,thewritesignalisgatedinternally
to prevent the write from proceeding.
The use of
BUSYlogicisnotrequiredordesirableforallapplications.
In some cases it may be useful to logically OR the
BUSYoutputstogether
and use any
BUSY indication as an interrupt source to flag the event of
an illegal or illogical operation.
Functional Description
The IDT70P269/259/249 are low-power CMOS 16K/8K/4K x 16
dual-port static RAMs. The two ports support user configurable standard
SRAM or time-multiplexed address and data (ADM) interfaces. The two
portsprovideseparatecontrol,address,andI/Opinsthatpermitindepen-
dent, asynchronous read and write access to any memory location. The
IDT70P269/259/249hasanautomaticpower-downfeaturecontrolledby
CS. The CS controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected (
CSHIGH).
Power Supply
The core voltage (VDD) can be 1.8V, 2.5V or 3.0V, as long as it is lower
than or equal to the I/O voltage. Each port can operate on independent
I/O voltages. This is determined by what is connected to the VDDIOL and
VDDIOR pins. The supported I/O standards are 1.8V/2.5V LVCMOS and
3.0V LVTTL.
The IDT70P269/259/249 includes power supply isolation functional-
itywhichaidssystempowermanagement. VDD,VDDIOR andVDDIOL canall
be independently powered up/down which allows either port and/or the
core to be powered down when not in use. If VDDIOX is powered down,
but VDD remains powered up all inputs to the core will be forced to
deassertedstatesatfullswingDCvaluestominimizeleakagecurrentand
active power consumption. If VDD is powered down but VDDIOX remain
powered up, all outputs for the port(s) in question will remain in the state
they were in prior to power down.
ADM Interface Read/Write Operation
The description of this section is applicable to either port when
configured in ADM mode.
Threecontrolsignals,
ADV,WE,andCSareusedtoperformtheread/
write operation. Address signals are first applied to the I/O bus along with
CS LOW. The addresses are loaded from the I/O bus in response to the
rising edge of the Address Latch Enable (
ADV) signal. It is necessary
to meet the set-up (tAVDS) and hold (tAVDH) times given in the AC
specifications with valid address information in order to properly latch the
addresses.
Once the address signals are latched in, a read operation is issued
when
WE stays HIGH. The I/O bus becomes HIGH-Z once the address
signals meeting tAVDH. The read data is driven on the I/O bus tOE after the
OE is asserted LOW, and held until tHZOE or tHZCS after the rising edge of
OE or CS, whichever comes first.
A write operation is issued when
WE is asserted LOW. The write
data is applied to the I/O bus right after address meets the hold time
(tAVDH). And write data is written with the rising edge of either
WE or
CS, whichever comes first, and meets data set-up (tSD) and hold (tHD)
times.
Awriteoperationisissuedwhen
WEisassertedLOW. Thewritedata
isappliedtotheI/Obusrightafteraddressmeetstheholdtime(tAVDH). And
write data is written with the rising edge of either
WE or CS, whichever
comes first, and meets data set-up (tSD) and hold (tHD) times.
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| 70P249L65BYGI8 | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 Low Power Dual-Port RAM IC RoHS:否 制造商:IDT 存儲(chǔ)容量: 組織: 訪問時(shí)間: 電源電壓-最大: 電源電壓-最小: 最大工作電流: 最大工作溫度: 最小工作溫度: 安裝風(fēng)格: 封裝 / 箱體: 封裝: |
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