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參數(shù)資料
| 型號： | 7016L20JGI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 16K X 9 DUAL-PORT SRAM, 20 ns, PQCC68 |
| 封裝： | 0.950 X 0.950 INCH, 0.170 INCH HEIGHT, GREEN, PLASTIC, LCC-68 |
| 文件頁數(shù)： | 5/20頁 |
| 文件大小： | 164K |
| 代理商： | 7016L20JGI |
6.42
IDT7016S/L
High-Speed 16K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
13
3190 drw 13
tDW
tAPS
ADDR"A"
tWC
DATAOUT "B"
MATCH
tWP
R/
W"A"
DATAIN "A"
ADDR"B"
tDH
VALID
(1)
MATCH
BUSY"B"
tBDA
VALID
tBDD
tDDD
(3)
tWDD
Timing Waveform of Read with BUSY(2,4,5) (M/S = VIH)
Timing Waveform of Write with BUSY(3)
NOTES:
1. tWH must be met for both
BUSY input (SLAVE) and output (MASTER).
2.
BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from Port "A".
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/
S=VIL.
2.
CEL = CER = VIL.
3.
OE = VIL for the reading port.
4. If M/
S=VIL (SLAVE), BUSY is an input. Then for this example BUSY“A” = VIH and BUSY“B” input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from Port "A".
3190 drw 14
R/
W"A"
BUSY"B"
tWP
tWB
R/
W"B"
tWH
(1)
(2)
,
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