Advance Information
MC68HC908MR16/MC68HC908MR32
—
Rev. 5.0
268
Serial Peripheral Interface Module (SPI)
MOTOROLA
Serial Peripheral Interface Module (SPI)
13.11 Low-Power Mode
The WAIT instruction puts the MCU in a low power-consumption standby
mode.
The SPI module remains active after the execution of a WAIT instruction.
In wait mode the SPI module registers are not accessible by the CPU.
Any enabled CPU interrupt request from the SPI module can bring the
MCU out of wait mode.
If SPI module functions are not required during wait mode, reduce power
consumption by disabling the SPI module before executing the WAIT
instruction.
To exit wait mode when an overflow condition occurs, enable the OVRF
bit to generate CPU interrupt requests by setting the error interrupt
enable bit (ERRIE). See
13.8 Interrupts
.
Since the SPTE bit cannot be cleared during a break with the BCFE bit
cleared, a write to the transmit data register in break mode does not
initiate a transmission nor is this data transferred into the shift register.
Therefore, a write to the SPDR in break mode with the BCFE bit cleared
has no effect.
13.12 I/O Signals
The SPI module has five I/O pins and shares four of them with a parallel
I/O port. The pins are:
MISO
—
Data received
MOSI
—
Data transmitted
SPSCK
—
Serial clock
SS
—
Slave select
The SPI has limited inter-integrated circuit (I
2
C) capability (requiring
software support) as a master in a single-master environment. To
communicate with I
2
C peripherals, MOSI becomes an open-drain output
when the SPWOM bit in the SPI control register is set. In I
2
C
communication, the MOSI and MISO pins are connected to a
bidirectional pin from the I
2
C peripheral and through a pullup resistor
to V
DD
.