
Serial Peripheral Interface Module (SPI)
Functional Description
MC68HC908MR16/MC68HC908MR32
—
Rev. 5.0
Advance Information
MOTOROLA
Serial Peripheral Interface Module (SPI)
251
SPI pins are shared by parallel I/O ports or have alternate functions. The
full name of an SPI pin reflects the name of the shared port pin or the
name of an alternate pin function. The generic pin names appear in the
text that follows.
Table 13-1
shows the full names of the SPI I/O pins.
13.5 Functional Description
Figure 13-1
shows the structure of the SPI module and
Figure 13-2
shows the locations and contents of the SPI I/O registers.
The SPI module allows full-duplex, synchronous, serial communication
between the microcontroller unit (MCU) and peripheral devices,
including other MCUs. Software can poll the SPI status flags or SPI
operation can be interrupt-driven. All SPI interrupts can be serviced by
the CPU.
13.5.1 Master Mode
The SPI operates in master mode when the SPI master bit, SPMSTR, is
set.
NOTE:
Configure the SPI modules as master or slave before enabling them.
Enable the master SPI before enabling the slave SPI. Disable the slave
SPI before disabling the master SPI. See
13.13.1 SPI Control Register
.
Only a master SPI module can initiate transmissions. Software begins
the transmission from a master SPI module by writing to the SPI data
register. If the shift register is empty, the byte immediately transfers to
the shift register, setting the SPI transmitter empty bit, SPTE. The byte
begins shifting out on the MOSI pin under the control of the serial clock.
See
Figure 13-3
.
Table 13-1. Pin Name Conventions
Generic
Pin Names:
MISO
MOSI
SPSCK
SS
Full
Pin Names:
PTF3/MISO
PTF2/MOSI
PTF0/SPSCK
PTF1/SS