Advance Information
MC68HC908MR16/MC68HC908MR32
—
Rev. 5.0
172
Pulse-Width Modulator for Motor Control (PWMMC)
MOTOROLA
Pulse-Width Modulator for Motor Control
PWMF
—
PWM Reload Flag
This read/write bit is set at the beginning of every reload cycle
regardless of the state of the LDOK bit. This bit is cleared by reading
PWM control register 1 with the PWMF flag set, then writing a logic 0
to PWMF. If another reload occurs before the clearing sequence is
complete, then writing logic 0 to PWMF has no effect.
1 = New reload cycle began.
0 = New reload cycle has not begun.
NOTE:
When PWMF is cleared, pending PWM CPU interrupts are cleared (not
including fault interrupts).
ISENS1 and ISENS0
—
Current Sense Correction Bits
These read/write bits select the top/bottom correction scheme as
shown in
Table 9-7
.
NOTE:
The ISENSx bits are not buffered. Changing the current sensing method
can affect the present PWM cycle.
LDOK
—
Load OK Bit
This read/write bit loads the prescaler bits of the PMCTL2 register and
the entire PMMODH/L and PWMVALH/L registers into a set of
buffers. The buffered prescaler divisor, PWM counter modulus value,
and PWM pulse will take effect at the next PWM load. Set LDOK by
reading it when it is logic 0 and then writing a logic 1 to it. LDOK is
Table 9-7. Correction Methods
Current Correction Bits
ISENS1 and ISENS0
Correction Method
00
01
Bits IPOL1, IPOL2, and IPOL3 are used for correction.
10
Current sensing on pins IS1, IS2, and IS3 occurs
during the dead-time.
11
Current sensing on pins IS1, IS2, and IS3 occurs at
the half cycle in center-aligned mode and at the end of
the cycle in edge-aligned mode.
1. The polarity of the ISx pin is latched when both the top and bottom PWMs are off. At
the 0% and 100% duty cycle boundaries, there is no dead-time, so no new current
value is sensed.
2. Current is sensed even with 0% and 100% duty cycle.