參數(shù)資料
型號: 5V80001PGGI
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: XO, clock
英文描述: 98.304 MHz, OTHER CLOCK GENERATOR, PDSO20
封裝: 4.40 MM, ROHS COMPLIANT, TSSOP-20
文件頁數(shù): 15/15頁
文件大小: 294K
代理商: 5V80001PGGI
IDT5V80001
MOST CLOCK INTERFACE
SYNTHESIZERS
IDT MOST CLOCK INTERFACE
9
IDT5V80001
REV S 083109
Figure 7: Duty Cycle Definitions
Figure 9: Propagation Delay
Figure 11: BYPASS Timing Definition
Figure 8: Power Up and PLL Lock Timing
Figure 10: Clock Timing
Figure 12: MOST Data–Clock Example
VDD
t
2
Clock
Output
t
1
0V
1.5 V
Duty Cycle, D=
t
2
t
1
tPD
FOT_IN
1.5 V
FOT_OUT
Note: RESET = H, BYPASS = H, OEM = L or H
tBLH
1.5 V
VDD
0V
FOT_OUT
tBHL
MOST_Din data
FOT_IN data
BYPASS
MOST_Din
FOT_IN
OEM
MOST_Din data
FOT_IN data
RESET
VDD
0V
VDD
0V
0 ms
Power Up
Time
VCO Ramp
Time
PLL Locked
tCLOCK
tDLOCK
Note: FOT_IN must be running and stable during VCO ramp time.
RCLK
t CDR
t SK
tJIT
FOT_IN
RCLK
INPUT_COPY
001
1
Coding
Violation
01
MOST Input
(retimed)
Recovered
Clock
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